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型號(hào)：	E5550F-DOW
廠商：	ATMEL CORP
元件分類：	通信及網(wǎng)絡(luò)
英文描述：	SPECIALTY TELECOM CIRCUIT, UUC7
封裝：	DIE-7
文件頁(yè)數(shù)：	650/1069頁(yè)
文件大?。?/td>	14303K
代理商：	E5550F-DOW

SAM4CP [DATASHEET]

43051E–ATPL–08/14

33.7.3 Master Mode Operations

When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate

generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip

select line to the slave and the serial clock signal (SPCK).

The SPI features two holding registers, the Transmit Data Register (SPI_TDR) and the Receive Data Register

(SPI_RDR), and a single Shift Register. The holding registers maintain the data flow at a constant rate.

After enabling the SPI, a data transfer starts when the processor writes to the SPI_TDR. The written data is immediately

transferred in the Shift Register and the transfer on the SPI bus starts. While the data in the Shift Register is shifted on

the MOSI line, the MISO line is sampled and shifted in the Shift Register. Data cannot be loaded in the SPI_RDR without

transmitting data. If there is no data to transmit, dummy data can be used (SPI_TDR filled with ones). When the

SPI_MR.WDRBT bit is set, new data cannot be transmitted if the SPI_RDR has not been read. If Receiving mode is not

required, for example when communicating with a slave receiver only (such as an LCD), the receive status flags in the

SPI status register (SPI_SR) can be discarded.

Before writing the SPI_TDR, the PCS field in the Mode Register (SPI_MR) must be set in order to select a slave.

If new data is written in SPI_TDR during the transfer, it is kept in the SPI_TDR until the current transfer is completed.

Then, the received data is transferred from the Shift Register to the SPI_RDR, the data in the SPI_TDR is loaded in the

Shift Register and a new transfer starts.

The transfer of data written in the SPI_TDR to the Shift Register is indicated by the Transmit Data Register Empty

(TDRE) bit in the SPI_SR. When new data is written in the SPI_TDR, this bit is cleared. The TDRE bit is used to trigger

the Transmit PDC channel.

The end of transfer is indicated by the TXEMPTY flag in the SPI_SR. If a transfer delay (DLYBCT) is greater than 0 for

the last transfer, TXEMPTY is set after the completion of this delay. The peripheral clock can be switched off at this time.

The transfer of received data from the Shift Register to the SPI_RDR is indicated by the Receive Data Register Full

(RDRF) bit in the SPI_SR. When the received data is read, the RDRF bit is cleared.

If the SPI_RDR has not been read before new data is received, the Overrun Error (OVRES) bit in SPI_SR is set. As long

as this flag is set, data is loaded in the SPI_RDR. The user has to read the status register to clear the OVRES bit.

, shows a block diagram of the SPI when operating in Master Mode.

Figure 33-6 on page 652

shows a flow

chart describing how transfers are handled.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
E5550F-S8	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DIT	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DOW	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-FP008	制造商:未知廠家制造商全稱:未知廠家功能描述:TRANSPONDER\|CMOS\|SOP\|8PIN\|PLASTIC
E5552	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder

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