914
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Moreover, it is possible to raise a flag only if there is a predefined change in the temperature. The user can define a
range of temperature or a threshold in the Temperature Compare Window register (ADC_TEMPCWR), and the mode of
comparison that can be programmed into ADC_TEMPMR by means of the TEMPCMPMOD field. These values define
the way the TEMPCHG flag is raised in ADC_ISR.
The TEMPCHG flag can be used to generate a temperature-dependent interrupt instead of the end-of-conversion
interrupt. In particular, the interrupt is generated only if the temperature sensor, as measured by the ADC, reports a
temperature value below, above, inside or outside programmable thresholds (see ADC_TEMPMR).
In any case, if TEMPON is set, the temperature can be read at anytime in ADC_CDR7 without any specific software
intervention.
40.6.10 VDDBU Measurement
The seventh ADC channel (CH6) of the ADC Controller is reserved for measurement of the VDDBU power supply pin.
For this channel, setting up, starting conversion, and other tasks must be performed the same way as for all other
channels. VDDBU is measured without any attenuation. This means that for VDDBU greater than the voltage reference
applied to the ADC, the digital output clamps to the maximum value.
40.6.11 Enhanced Resolution Mode and Digital Averaging Function
The enhanced resolution mode is enabled if LOWRES is cleared in ADC_MR, and the OSR field is set to 1, 2 in
ADC_EMR. The enhancement is based on a digital averaging function.
FREERUN must be set to 0 when digital averaging is used (OSR differs from 0 in ADC_EMR).
There is no averaging on the last index channel if the measure is triggered by an RTC event (see
Section 40.6.9
”Temperature Sensor”
).
In enhanced resolution mode, the ADC Controller trades conversion speed for quantization noise by averaging multiple
samples, thus providing a digital low-pass filter function.
If 1-bit enhancement resolution is selected (OSR = 1 in ADC_EMR), the ADC effective sample rate is the maximum ADC
sample rate divided by 4; therefore, the oversampling ratio is 4.
When the 2-bit enhancement resolution is selected (OSR = 2 in ADC_EMR), the ADC effective sample rate is the
maximum ADC sample rate divided by 16 (oversampling ratio is 16).
The selected oversampling ratio applies to all enabled channels except for the temperature sensor channel when
triggered by an RTC event.
The average result is valid into the ADC_CDRx register (x corresponding to the index of the channel) only if EOCn flag is
set in ADC_ISR and OVREn flag is cleared in ADC_OVER. The average result for all channels is valid in ADC_LCDR
only if DRDY is set and GOVRE is cleared in ADC_ISR.
Note that ADC_CDRx are not buffered. Therefore, when an averaging sequence is ongoing, the value in these registers
changes after each averaging sample. On the other hand, overrun flags in ADC_OVER rise as soon as the first sample of
an averaging sequence is received and thus the previous averaged value is not read (even if the new averaged value is
not ready).
In consequence, when an overrun flag rises in ADC_OVER, the previous unread data is lost but the data has not been
overwritten by the new averaged value, as the averaging sequence concerning this channel may still be on-going.
40.6.11.1 Averaging Function versus Trigger Events
The samples can be defined in different ways for the averaging function depending on the configuration of the ASTE bit
in ADC_EMR and the USEQ bit in ADC_MR.
When USEQ is cleared, there are two ways to generate the averaging through the trigger event. If ASTE bit is cleared in
ADC_EMR, every trigger event generates one sample for each enabled channel as described in
Figure 40-9, "Digital
Averaging Function Waveforms over multiple trigger events"
. Therefore, four trigger events are requested to get the
result of averaging if OSR = 1.