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型號(hào)：	E5550F-DOW
廠商：	ATMEL CORP
元件分類：	通信及網(wǎng)絡(luò)
英文描述：	SPECIALTY TELECOM CIRCUIT, UUC7
封裝：	DIE-7
文件頁(yè)數(shù)：	57/1069頁(yè)
文件大?。?/td>	14303K
代理商：	E5550F-DOW

SAM4CP [DATASHEET]

43051E–ATPL–08/14

12.4.1.11 Execution Program Status Register

The EPSR contains the Thumb state bit, and the execution state bits for either the

(IT) instruction, or the

Interruptible-

Continuable Instruction

(ICI) field for an interrupted load multiple or store multiple instruction.

Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write

the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR value in the

stacked PSR to indicate the operation that is at fault. See

“Exception Entry and Return”

ICI: Interruptible-continuable Instruction

When an interrupt occurs during the execution of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH, or VPOP instruction, the

– Stops the load multiple or store multiple instruction operation temporarily.

– Stores the next register operand in the multiple operation to EPSR bits[15:12].

After servicing the interrupt, the processor:

– Returns to the register pointed to by bits[15:12].

– Resumes the execution of the multiple load or store instruction.

When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero.

IT: If-Then Instruction

Indicates the execution state bits of the

instruction.

The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The con-

ditions for the instructions are either all the same, or some can be the inverse of others. See

for more information.

T: Thumb State

The Cortex-M4 processor only supports the execution of instructions in Thumb state. The following can clear the T bit to 0:

– Instructions BLX, BX and POP{PC}.

– Restoration from the stacked xPSR value on an exception return.

– Bit[0] of the vector value on an exception entry or reset.

Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See

for more information.

12.4.1.12 Exception Mask Registers

The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might

impact on timing critical tasks.

To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value

of PRIMASK or FAULTMASK. See

for more information.

相關(guān)PDF資料	PDF描述
E5530H-230-S8	SPECIALTY TELECOM CIRCUIT, PDSO8
E5530H-230-DOW	SPECIALTY TELECOM CIRCUIT, UUC
ECM2A5C3A12-29.939MTR	QUARTZ CRYSTAL RESONATOR, 29.939 MHz
ECM2A5C3A32-34.400M	QUARTZ CRYSTAL RESONATOR, 34.4 MHz
ED1702N	NPN general purpose transistor

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
E5550F-S8	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DIT	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DOW	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-FP008	制造商:未知廠家制造商全稱:未知廠家功能描述:TRANSPONDER\|CMOS\|SOP\|8PIN\|PLASTIC
E5552	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder

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