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型號(hào)：	E5550F-DOW
廠商：	ATMEL CORP
元件分類：	通信及網(wǎng)絡(luò)
英文描述：	SPECIALTY TELECOM CIRCUIT, UUC7
封裝：	DIE-7
文件頁(yè)數(shù)：	943/1069頁(yè)
文件大小：	14303K
代理商：	E5550F-DOW

SAM4CP [DATASHEET]

43051E–ATPL–08/14

To have a sequential increment, the counter value must be programmed with the value programmed for the previous

fragment + 2

(or less for the first fragment).

All AES_IVRx fields must be programmed to take into account the possible carry propagation.

41.4.2 Double Input Buffer

The AES_IDATARx can be double-buffered to reduce the runtime of large files.

This mode allows writing a new message block when the previous message block is being processed. This is only

possible when DMA accesses are performed (SMOD = 0x2).

The DUALBUFF bit in AES_MR must be set to 1 to access the double buffer.

41.4.3 Start Modes

The SMOD field in the AES_MR allows selection of the encryption (or decryption) start mode.

41.4.3.1 Manual Mode

The sequence order is as follows:

Write the AES_MR with all required fields, including but not limited to SMOD and OPMOD.

Write the 128-bit/192-bit/256-bit key in the AES_KEYWRx.

Write the initialization vector (or counter) in the AES_IVRx.

The AES_IVRx concern all modes except ECB.

Set the bit DATRDY (Data Ready) in the AES Interrupt Enable register (AES_IER), depending on whether an

interrupt is required or not at the end of processing.

Write the data to be encrypted/decrypted in the authorized AES_IDATARx (See

In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in

In 32-, 16- and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3 is not

allowed and may lead to errors in processing.

Set the START bit in the AES Control register (AES_CR) to begin the encryption or the decryption process.

When processing completes, the DATRDY flag in the AES Interrupt Status Register (AES_ISR) is raised. If an

interrupt has been enabled by setting the DATRDY bit in the AES_IER, the interrupt line of the AES is activated.

When software reads one of the AES_ODATARx, the DATRDY bit is automatically cleared.

Authorized Input Data Registers

Operation Mode

Input Data Registers to Write

AES_IDATAR0 and AES_IDATAR1

相關(guān)PDF資料	PDF描述
E5530H-230-S8	SPECIALTY TELECOM CIRCUIT, PDSO8
E5530H-230-DOW	SPECIALTY TELECOM CIRCUIT, UUC
ECM2A5C3A12-29.939MTR	QUARTZ CRYSTAL RESONATOR, 29.939 MHz
ECM2A5C3A32-34.400M	QUARTZ CRYSTAL RESONATOR, 34.4 MHz
ED1702N	NPN general purpose transistor

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
E5550F-S8	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DIT	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-DOW	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder
E5551A-FP008	制造商:未知廠家制造商全稱:未知廠家功能描述:TRANSPONDER\|CMOS\|SOP\|8PIN\|PLASTIC
E5552	制造商:未知廠家制造商全稱:未知廠家功能描述:Transponder

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