350
SAM4CP [DATASHEET]
43051E–ATPL–08/14
22.
Enhanced Embedded Flash Controller (EEFC)
22.1
Description
The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus.
Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking
and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash
descriptor definition that informs the system about the Flash organization, thus making the software generic.
22.2
Embedded Characteristics
Interface of the Flash Block with the 32-bit Internal Bus
Increases Performance in Thumb-2 Mode with 128-bit or 64-bit wide Memory Interface up to 100 MHz
Code Loop Optimization
128 Lock Bits, Each Protecting a Lock Region
2 General-purpose GPNVM Bits
One-by-one Lock Bit Programming
Commands Protected by a Keyword
Erase the Entire Flash
Erase by Plane
Erase by Sector
Erase by Pages
Possibility of Erasing before Programming
Locking and Unlocking Operations
ECC Single and Multiple Error Flags Report
Possibility to Read the Calibration Bits
22.3
Product Dependencies
22.3.1 Power Management
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller has no
effect on its behavior.
22.3.2 Interrupt Sources
The EEFC interrupt line is connected to the interrupt controller. Using the EEFC interrupt requires the interrupt controller
to be programmed first. The EEFC interrupt is generated only if the value of bit EEFC_FMR.FRDY is 1.
Table 22-1.
Peripheral IDs
Instance
ID
EFC
6