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SAM4CP [DATASHEET]
43051E–ATPL–08/14
In
Figure 7-1
, ‘Code’ means ‘Program Code over I-Code bus’ and ‘Program Data over D-Code bus’.
SRAM1 shown in the mapping above can be seen at the address 0x20080000 (through S-bus) and the address
0x00000000 (through I/D Bus) for Core 1. Instruction fetch from Core 1 to the SRAM address range is possible but leads
to reduced performance due to the fact that instructions and read/write data go through the System Bus (S-Bus).
Maximum performance for Core 1 is obtained by mapping the instruction code to the address 0x00000000 (SRAM1
through I/D-Code) and read/write data from the address 0x20100000 (SRAM2 through S-Bus).
For Core 0 (Application Core), maximum performance is achieved when the instruction code is mapped to the flash
address and read/write data is mapped into SRAM0.
Each cores can access the following memories and peripherals:
Core 0 (Application Core):
All internal memories
All internal peripherals
Core 1 (Coprocessor Core):
All internal memories
All internal peripherals
Note that Peripheral DMA 0 on Matrix 0 cannot access SRAM1 or SRAM2, Peripheral DMA 1 on Matrix 1 cannot access
SRAM0, SRAM2 or SRAM0 can be the Data RAM for Inter-core Communication.
If the Core 1 is not to be used (Clock Stopped and Reset active), all the peripherals, SRAM1 and SRAM2 of the Sub-
system 1 can be used by the Application Core (Core 0) as long as the peripheral bus clock and reset are configured.
Detailed Memory Mapping and Memory Access versus Matrix Masters/Slaves is given in the “Bus Matrix (MATRIX)”
section of this datasheet.