
403
SAM4CP [DATASHEET]
43051E–ATPL–08/14
26.2.1.2 Matrix 0 Slaves
The Bus Matrix of the SAM4CP manages the slaves listed in
Table 26-2
. Each slave has its own arbiter providing a
dedicated arbitration per slave.
26.2.1.3 Master to Slave Access (Matrix 0)
Table 26-3
gives valid paths for master to slave access on Matrix 0. The paths shown as “-” are forbidden or not wired,
e.g. access from the Cortex-M4 S Bus to the Internal ROM.
26.2.1.4 Accesses through Matrix 0
CM4P0 I/D Bus access to:
FLASH, ROM
FLASH through Cache Controller CMCC0 (respectively through 0x11000000 to 0x11FFFFFF and
0x13000000 to 0x16FFFFFF)
CMP4P0 S Bus access to:
SRAM0, SRAM1 through Matrix1, SRAM2 through Matrix1
CPKCC
Table 26-2.
List of Bus Matrix Slaves
Slave 0
Internal SRAM0
Slave 1
Internal ROM
Slave 2
Internal Flash
Slave 3
Reserved
Slave 4
Peripheral Bridge 0
Slave 5
CPKCC RAM and ROM
Slave 6
Matrix1
Slave 7
CMCC0
Table 26-3.
Matrix 0 Master to Slave Access
Slaves
Masters
0
1
2
3
4
5
6
Cortex-M4
I/D Bus
Cortex-M4
S Bus
PDC0
ICM
Matrix1
Reserved
CMCC0
0
Internal SRAM0
-
X
X
X
X
-
-
1
Internal ROM
X
-
X
X
-
-
-
2
Internal Flash
X
-
-
X
X
-
X
3
Reserved
-
-
-
-
-
-
-
4
Peripheral Bridge 0
-
X
X
-
X
-
-
5
CPKCC SRAM, ROM
-
X
-
X
-
-
-
6
Matrix1
-
X
-
X
-
-
-
7
CMCC0
X
-
-
-
-
-
-