334
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Figure 20-5.
Low-Power Debouncer (Push-to-Make Switch, Pull-up Resistors)
Figure 20-6.
Low-Power Debouncer (Push-to-Break Switch, Pull-down Resistors)
The debouncing period duration is configurable.The period is identical for all debouncers (i.e., the duration cannot be
adjusted separately for each debouncer). The number of successive identical samples to wake up the system can be
configured from 2 up to 8 in the LPDBC field of SUPC_WUMR. The period of time between two samples can be
configured by programming the TPERIOD field in the RTC_MR. Power parameters can be adjusted by modifying the
period of time in the THIGH field in RTC_MR.
The wake-up polarity of the inputs can be independently configured by writing WKUPT0/WKUPT10/WKUPT14
/WKUPT15 fields in SUPC_WUMR.
In order to determine which wake-up/tamper pin triggers the system wake-up, a status flag is associated for each low-
power debouncer. These flags can be read in the SUPC_SR.
A debounce event (tamper detection) can perform an immediate clear (0 delay) on first half the general-purpose backup
registers (GPBR). The LPDBCCLR bit must be set in
Section 20.6.5 ”Supply Controller Mode Register”
and it is possible
to individually disable the clear capability for TMP1/TMP2/TMP3 by writing a 1 in the corresponding bit
DISTMPCLR1/2/3.
Note that it is not mandatory to use the RTCOUT0 pin when using the WKUP0/WKUP10/WKUP14/WKUP15 pins as
tampering inputs (TMP0/TMP1/TMP2/TMP3) in any mode. Using RTCOUT0 pin provides a “sampling mode” to further
reduce the power consumption of the tamper detection circuitry. If RTCOUT0 is not used, the RTC must be configured to
create an internal sampling point for the debouncer logic. The period of time between two samples can be configured by
programming the TPERIOD field in the RTC_MR.
MCU
WKUP0/TMP0
WKUPx/TMPx
RTCOUT0
Pull-Up
Resistor
Pull-Up
Resistor
GND
GND
GND
MCU
WKUP0/TMP0
WKUPx/TMPx
RTCOUT0
Pull-Down
Resistors
GND
GND
GND