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SAM4CP [DATASHEET]
43051E–ATPL–08/14
To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. The
example below shows instructions with the instruction width suffix.
BCS.W label ;creates
;branch
ADDS.W R0, R0, R1 ;creates a 32-bit instruction even though the same
;operation can be done by a 16-bit instruction
a
32-bit
instruction
even
for
a
short
12.6.4 Memory Access Instructions
The table below shows the memory access instructions:
12.6.4.1 ADR
Load PC-relative address.
Syntax
ADR{
cond
}
Rd
,
label
where:
cond
is an optional condition code, see
“Conditional Execution”
.
Rd
is the destination register.
label
is a PC-relative expression. See
“PC-relative Expressions”
.
Operation
ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register.
ADR produces position-independent code, because the address is PC-relative.
If ADR is used to generate a target address for a BX or BLX instruction, ensure that bit[0] of the address generated is set
to 1 for correct execution.
Values of
label
must be within the range of -4095 to +4095 from the address in the PC.
Note:
The user might have to use the .W suffix to get the maximum offset range or to generate addresses that are not
word-aligned. See
“Instruction Width Selection”
.
Table 12-17. Memory Access Instructions
Mnemonic
Description
ADR
Load PC-relative address
CLREX
Clear Exclusive
LDM{mode}
Load Multiple registers
LDR{type}
Load Register using immediate offset
LDR{type}
Load Register using register offset
LDR{type}T
Load Register with unprivileged access
LDR
Load Register using PC-relative address
LDRD
Load Register Dual
LDREX{type}
Load Register Exclusive
POP
Pop registers from stack
PUSH
Push registers onto stack
STM{mode}
Store Multiple registers
STR{type}
Store Register using immediate offset
STR{type}
Store Register using register offset
STR{type}T
Store Register with unprivileged access
STREX{type}
Store Register Exclusive