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659
SAM4CP [DATASHEET]
43051E–ATPL–08/14
33.7.5 Register Write Protection
To prevent any single software error from corrupting SPI behavior, certain registers in the address space can be write-
protected by setting the WPEN bit in the
”SPI Write Protection Mode Register”
(SPI_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the
”SPI Write Protection Status Register”
(SPI_WPSR) is set and the WPVSRC field indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading SPI_WPSR.
The following registers can be write-protected:
Section 33.8.2 ”SPI Mode Register”
Section 33.8.9 ”SPI Chip Select Register”
33.8
Serial Peripheral Interface (SPI) User Interface
Table 33-5.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Control Register
SPI_CR
Write-only
–
0x04
Mode Register
SPI_MR
Read/Write
0x0
0x08
Receive Data Register
SPI_RDR
Read-only
0x0
0x0C
Transmit Data Register
SPI_TDR
Write-only
–
0x10
Status Register
SPI_SR
Read-only
0x000000F0
0x14
Interrupt Enable Register
SPI_IER
Write-only
–
0x18
Interrupt Disable Register
SPI_IDR
Write-only
–
0x1C
Interrupt Mask Register
SPI_IMR
Read-only
0x0
0x20 - 0x2C
Reserved
–
–
–
0x30
Chip Select Register 0
SPI_CSR0
Read/Write
0x0
0x34
Chip Select Register 1
SPI_CSR1
Read/Write
0x0
0x38
Chip Select Register 2
SPI_CSR2
Read/Write
0x0
0x3C
Chip Select Register 3
SPI_CSR3
Read/Write
0x0
0x40 - 0xE0
Reserved
–
–
–
0xE4
Write Protection Control Register
SPI_WPMR
Read/Write
0x0
0xE8
Write Protection Status Register
SPI_WPSR
Read-only
0x0
0x00EC - 0x00F8
Reserved
–
–
–
0x00FC
Reserved
–
–
–
0x100 - 0x124
Reserved for PDC Registers
–
–
–