402
SAM4CP [DATASHEET]
43051E–ATPL–08/14
26.
Bus Matrix (MATRIX)
26.1
Description
The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths
between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix
interconnects AHB masters to
AHB slaves. The normal latency to connect a master to a slave is one cycle except for the
default master of the accessed slave which is connected directly (zero cycle latency).
26.2
Embedded Characteristics
One decoder for each master.
Support for long bursts of 32, 64, 128 beats and up to the 256-beat word burst AHB limit.
Enhanced programmable mixed arbitration for each slave.
Round-robin.
Fixed priority.
Latency quality of service.
Programmable default master for each slave.
No default master.
Last accessed default master.
Fixed default master.
Deterministic maximum access latency for masters.
Zero or one cycle arbitration latency for the first access of a burst.
Bus lock forwarding to slaves.
Master number forwarding to slaves.
Write protection of user interface registers.
26.2.1 Matrix 0
26.2.1.1 Matrix 0 Masters
The Bus Matrix 0, which corresponds to the sub-system 0 (Core 0 - CM4P0) manages the masters listed in
Table 26-1
.
Each master can perform an access to an available slave concurrently with other masters.
Each master has its own specifically-defined decoder. In order to simplify the addressing, all the masters have the same
decodings.
Table 26-1.
List of Bus Matrix Masters
Master 0
Cortex-M4 Instruction/Data (CM4P0 I/D Bus)
Master 1
Cortex-M4 System (CM4P0 S Bus)
Master 2
Peripheral DMA Controller 0 (PDC0)
Master 3
Integrity Check Module (ICM)
Master 4
Matrix1
Master 5
Reserved
Master 6
CMCC0