
697
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Clock Synchronization/Stretching
In both read and write modes, it may occur that TWI_THR/TWI_RHR buffer is not filled/emptied before the
emission/reception of a new character. In this case, to avoid sending/receiving undesired data, clock
stretching/synchronization mechanism is implemented.
Clock Stretching in Read Mode
The clock is tied low during the acknowledge phase if the internal shifter is empty and if a STOP or REPEATED START
condition was not detected. It is tied low until the internal shifter is loaded.
Figure 34-29
describes the clock stretching in Read mode.
Figure 34-29. Clock Stretching in Read Mode
Notes: 1.
TXRDY is reset when data has been written in the TWI_THR to the internal shifter and set when this data
has been acknowledged or non acknowledged.
At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED START + an address
different from SADR.
SCLWS is automatically set when the clock stretching mechanism is started.
2.
3.
DATA1
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
SCLWS
TXRDY
SVACC
SVREAD
TWCK
TWI_THR
TXCOMP
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register
Ack or Nack from the master
DATA0
DATA2
1
2
1
CLOCK is tied low by the TWI
as long as THR is empty
S
SADR
R
DATA0
A
A
DATA1
A
DATA2
NA
S
XXXXXXX
2
Write THR
As soon as a START is detected