275
SAM4CP [DATASHEET]
43051E–ATPL–08/14
15.5.2 Reset Controller Status Register
Name:
RSTC_SR
Address:
0x400E1404
Access:
Read-only
URSTS: User Reset Status
A high-to-low transition of the NRST pin sets the URSTS bit. This transition is also detected on the MCK rising edge. If the user
reset is disabled (URSTEN = 0 in RSTC_MR) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR,
the URSTS
bit triggers an interrupt. Reading the RSTC_SR resets the URSTS bit and clears the interrupt.
0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.
1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
RSTTYP: Reset Type
This field reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
NRSTL: NRST Pin Level
This bit registers the NRST pin level sampled on each Master Clock (MCK) rising edge.
SRCMP: Software Reset Command in Progress
When set, this bit indicates that a software reset command is in progress and that no further software reset should be performed
until the end of the current one. This bit is automatically cleared at the end of the current software reset.
0 = No software command is being performed by the reset controller. The reset controller is ready for a software command.
1 = A software reset command is being performed by the reset controller. The reset controller is busy.
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
16
SRCMP
NRSTL
15
–
14
–
13
–
12
–
11
–
10
9
8
RSTTYP
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
URSTS
Value
Name
Description
0
General Reset
First power-up Reset
1
Backup Reset
Return from Backup Mode
2
Watchdog Reset
Watchdog fault occurred
3
Software Reset
Processor reset required by the software
4
User Reset
NRST pin detected low