540
SAM4CP [DATASHEET]
43051E–ATPL–08/14
The procedure and conditions to enter wait mode and the circuitry to exit wait mode are strictly the same as fast startup
(see
Section 30.10 ”Main Processor Fast Startup”
).
30.12 Coprocessor Sleep Mode
The coprocessor enters Sleep Mode by executing the WaitForInterrupt (WFI) instruction of the coprocessor. Any enabled
interrupt can wake the processor up.
30.13 Main Clock Failure Detector
The clock failure detector monitors the main crystal oscillator or ceramic resonator-based oscillator to identify an eventual
failure of this oscillator.
The clock failure detector can be enabled or disabled by bit CFDEN in CKGR_MOR. After a VDDCORE reset, the
detector is disabled. However, if the oscillator is disabled (MOSCXTEN = 0), the detector is disabled too.
A failure is detected by means of a counter incrementing on the main oscillator clock edge and timing logic clocked on
the slow RC oscillator controlling the counter. Thus, the slow RC oscillator must be enabled.
The counter is cleared when the slow RC oscillator clock signal is low and enabled when the signal is high. Thus the
failure detection time is 1 slow RC oscillator clock period. If, during the high level period of the slow RC oscillator clock
signal, less than 8 fast crystal oscillator clock periods have been counted, then a failure is reported.
If a failure of the main oscillator is detected, bit CFDEV in PMC_SR indicates a failure event and generates an interrupt if
the corresponding interrupt source is enabled. The interrupt remains active until a read occurs in PMC_SR. The user can
know the status of the clock failure detection at any time by reading the CFDS bit in PMC_SR.
Figure 30-4.
Clock Failure Detection (Example)
If the main oscillator is selected as the source clock of MAINCK (MOSCSEL in CKGR_MOR = 1), and if the Master Clock
Source is PLLACK or PLLBCK (CSS = 2), a clock failure detection automatically forces MAINCK to be the source clock
for the master clock (MCK).Then, regardless of the PMC configuration, a clock failure detection automatically forces the
Fast RC Oscillator to be the source clock for MAINCK. If the Fast RC Oscillator is disabled when a clock failure detection
occurs, it is automatically re-enabled by the clock failure detection mechanism.
It takes 2 slow clock RC oscillator cycles to detect and switch from the main oscillator, to the Fast RC Oscillator if the
source MCK is Main Clock (MAINCK), or three slow clock RC oscillator cycles if the source of MCK is PLLACK or
PLLBCK.
The user can know the status of the clock failure detector at any time by reading the FOS bit in PMC_SR.
This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault
Output Clear Register (PMC_FOCR).
Main Crystal Clock
SLCK
Note: ratio of clock periods is for illustration purposes only
CDFEV
CDFS
Read PMC_SR