參數(shù)資料
型號： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 96/174頁
文件大?。?/td> 1261K
代理商： DS3131
DS3131
28 of 174
4. MEMORY MAP
4.1 Introduction
All addresses within the memory map are on dword boundaries, even though all internal device
configuration registers are only one word (16 bits) wide. The memory map consumes an address range of
4kb (12 bits). When the PCI bus is the host (i.e., the local bus is in bridge mode), the actual 32-bit PCI
bus addresses of the internal device configuration registers are obtained by adding the DC base address
value in the PCI device-configuration memory-base address register (Section 10.2) to the offset listed in
Sections 4.1 to 4.10. When an external host is configuring the device through the local bus (i.e., the local
bus is in the configuration mode), the offset is 0h and the host on the local bus uses the 16-bit addresses
listed in Sections 4.2 to 4.10.
Table 4-A. Memory Map Organization
REGISTER
PCI HOST [OFFSET
FROM DC BASE]
LOCAL BUS HOST
(16-BIT ADDRESS)
SECTION
General Configuration Registers
(0x000)
(00xx)
4.2
Receive Port Registers
(0x1xx)
(01xx)
Transmit Port Registers
(0x2xx)
(02xx)
Receive HDLC Control Registers
(0x3xx)
(03xx)
Transmit HDLC Control Registers
(0x4xx)
(04xx)
BERT Registers
(0x5xx)
(05xx)
Receive DMA Registers
(0x7xx)
(07xx)
Transmit DMA Registers
(0x8xx)
(08xx)
FIFO Registers
(0x9xx)
(09xx)
PCI Configuration Registers for Function 0
(PIDSEL)
(0Axx)
PCI Configuration Registers for Function 1
(PIDSEL)
(0Bxx)
4.2 General Configuration Registers (0xx)
OFFSET/
ADDRESS
NAME
REGISTER
SECTION
0000
MRID
Master Reset and ID Register
5.1
0010
MC
Master Configuration
0020
SM
Master Status Register
0024
ISM
Interrupt Mask Register for SM
0028
SDMA
Status Register for DMA
002C
ISDMA
Interrupt Mask Register for SDMA
0040
LBBMC
Local Bus Bridge Mode Control Register
0050
TEST
Test Register
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