參數(shù)資料
型號： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 140/174頁
文件大?。?/td> 1261K
代理商： DS3131
DS3131
68 of 174
8.2 FIFO Register Description
Register Name:
RFSBPIS
Register Description:
Receive FIFO Starting Block Pointer Indirect Select
Register Address:
0900h
Bit #
7
6
5
4
3
2
1
0
Name
reserved
HCID5
HCID4
HCID3
HCID2
HCID1
HCID0
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
IAB
IARW
reserved
Default
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 5/HDLC Channel ID (HCID0 to HCID5)
000000 (00h) = HDLC channel number 1
100111 (27h) = HDLC channel number 40
Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the current internal receive
block pointer, the host should write this bit to 1. This causes the device to begin obtaining the data from the
channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready
to be read from the RFSBP register, the IAB bit is set to 0. When the host wishes to write data to set the internal
receive starting block pointer, the host should write this bit to 0. This causes the device to take the data that is
currently present in the RFSBP register and write it to the channel location indicated by the HCID bits. When the
device has completed the write, the IAB is set to 0.
Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set
to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is
ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the
write operation has completed.
Register Name:
RFSBP
Register Description:
Receive FIFO Starting Block Pointer
Register Address:
0904h
Bit #
7
6
5
4
3
2
1
0
Name
RSBP7
RSBP6
RSBP5
RSBP4
RSBP3
RSBP2
RSBP1
RSBP0
Default
Bit #
15
14
13
12
11
10
9
8
Name
reserved
RSBP8
Default
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 8/Starting Block Pointer (RSBP0 to RSBP8). These bits determine which of the 512 blocks within the
receive FIFO the host wants the device to configure as the starting block for a particular HDLC channel. Any of
the blocks within a chain of blocks for an HDLC channel can be configured as the starting block. When these nine
bits are read, they report the current block pointer being used to write data into the receive FIFO from the HDLC
controllers.
000000000 (000h) = use block 0 as the starting block
111111111 (1ffh) = use block 511 as the starting block
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