參數(shù)資料
型號: DS3131
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Telecom IC:Other
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 6/174頁
文件大?。?/td> 1261K
代理商: DS3131
DS3131
103 of 174
DMA Updates to the Done Queue
The host has two options for when the transmit DMA should write descriptors that have completed
transmission to the done queue. On a channel-by-channel basis, through the done-queue select (DQS) bit
in the transmit DMA configuration RAM, the host can condition the DMA to:
1) Write to the done queue only when the complete HDLC packet has been transmitted (DQS = 0).
2) Write to the done queue when each data buffer has been transmitted (DQS = 1).
The status field in the done-queue descriptor is configured based on the setting of the DQS bit.
If DQS = 0, it is set to 000 when a packet has successfully completed transmission of the status field. If
DQS = 1, it is set to 001 when the first data buffer has successfully completed transmission of the status
field. The status field is set to 010 when each middle buffer (i.e., the second through the next to last) has
successfully completed transmission. The status field is set to 011 when the last data buffer of a packet
has successfully completed transmission.
Error Conditions
While processing packets for transmission, the DMA can encounter a number of error conditions, which
include the following:
= PCI error (an abort error)
= transmit FIFO underflow
= channel is disabled (CHEN = 0) in the transmit DMA configuration RAM
= channel number discrepancy between the pending queue and the packet descriptor
= Byte count of 0 Bytes in the packet descriptor
If any of these errors occur, the transmit DMA automatically disables the affected channel by setting the
channel enable (CHEN) bit in the transmit DMA configuration RAM to 0. Then it writes the current
descriptor into the done queue with the appropriate error status, as shown in Table 9-H.
Table 9-H. Done-Queue Error-Status Conditions
PACKET
STATUS
ERROR DESCRIPTION
100
Software provisioning error; this channel was not enabled
101
Descriptor error; either byte count = 0 or channel code inconsistent with pending queue
110
PCI error; either parity or abort
111
Transmit FIFO error; it has underflowed
Since the transmit DMA has disabled the channel, any remaining queued descriptors are not transmitted
and are written to the done queue with a packet status of 100 (i.e., reporting that the channel was not
enabled). At this point the host has two options. Option 1: It can wait until all of the remaining queued
descriptors are written to the done queue with an errored status, manually re-enable the channel by
setting the CHEN bit to 1, and then re-queue all of the affected packets. Option 2: As soon as it detects
an errored status, it can force the channel active again by setting the channel reset (CHRST) bit to 1 for
the next descriptor that it writes to the pending queue for the affected channel. As soon as the transmit
DMA detects that the CHRST is set to 1, it re-enables the channel by forcing the CHEN bit to 1. The
DMA does not re-enable the channel until it has finished writing all of the previously queued descriptors
to the done queue. Then the host can collect the errored descriptors as they arrive in the done queue and
re-queue them for transmission by writing descriptors to the pending queue, so the transmit DMA knows
where to find the packets that did not get transmitted (Note: The host must set the next pending
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