參數(shù)資料
型號： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 48/174頁
文件大?。?/td> 1261K
代理商： DS3131
DS3131
141 of 174
11.1.1
PCI Bridge Mode
In the PCI bridge mode, data from the PCI bus can be transferred to the local bus. The local bus acts as a
“master” and creates all the necessary signals to control the bus. The user must configure the local bus
bridge mode control register (LBBMC), which is described in Section 11.2.
With 20 address lines, the local bus can address 1MB address space. The host on the PCI bus determines
where to map this 1MB address space within the 32-bit address space of the PCI bus by configuring the
base address in the PCI configuration registers (Section 10).
Bridge Mode 8-Bit and 16-Bit Access
During a bus access by the host, the local bus can determine how to map the four possible byte positions
from/to the PCI bus to/from the local bus data bus (LD) pins by examining the PCBE signals and the
local bus width (LBW) control bit that resides in the local bus bridge mode control (LBBMC) register. If
the local bus is used as an 8-bit bus (LBW = 1), the host must only assert one of the PCBE signals. The
PCI data is mapped to/from the LD[7:0] signal lines; the LD[15:0] signal lines remain inactive. The local
bus block drives the A0 and A1 address lines according to the assertion of the PCBE signals by the host.
See Table 11-B for details. If the host asserts more than one of the PCBE signals when the local bus is
configured as an 8-bit bus, the local bus rejects the access and the PCI block returns a target abort to the
host. See Section 10 for details about a target abort.
Table 11-B. Local Bus 8-Bit Width Address,
LBHE
LBHE Setting
PCBE
PCBE [3:0]
A1
A0
LBHE
1110
0
1
1101
0
1
1011
1
0
1
0111
1
Note 1:
All other possible states for
PCBE cause the device to return a target abort to the host.
Note 2:
The 8-bit data picked from the PCI bus is routed/sampled to/from the LD[7:0] signal lines.
Note 3:
If no
PCBE signals are asserted during an access, a target abort is not returned and no transaction occurs on the local bus.
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