參數(shù)資料
型號： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 52/174頁
文件大?。?/td> 1261K
代理商： DS3131
DS3131
145 of 174
11.2 Local Bus Bridge Mode Control Register Description
Register Name:
LBBMC
Register Description:
Local Bus Bridge Mode Control
Register Address:
0040h
Note:
This register can only be accessed through the PCI bus and therefore only in the PCI bridge mode. In configuration mode, this register
cannot be accessed. It is set to all zeros upon a hardware reset issued through the
PRST pin. It is not affected by a software reset issued
through the RST control bit in the master reset and ID (MRID) register.
Bit #
7
6
5
4
3
2
1
0
Name
reserved
LBW
LRDY3
LRDY2
LRDY1
LRDY0
LARBE
LCLKE
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
reserved
LAT3
LAT2
LAT1
LAT0
Default
0
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Local Bus Clock Enable (LCLKE)
0 = three-state the LCLK output signal pin
1 = allow LCLK to appear at the pin
Bit 1/Local Bus Arbitration Enable (LARBE). When enabled, the LHOLD (LBR), LBGACK, and LHLDA
(LBG) signal pins are active and the proper arbitration handshake sequence must occur for a proper bus
transaction. When disabled, the LHOLD (LBR), LBGACK, and LHLDA (LBG) signal pins are deactivated and
bus arbitration on the local bus is not invoked. Also, the arbitration timer is enabled (see the description of the
LAT0 to LAT3 bits) when LARBE is set to 1.
0 = local bus arbitration is disabled
1 = local bus arbitration is enabled
Bit 2/Local Bus Ready Control Bit 0 (LRDY0). LSB
Bit 3/Local Bus Ready Control Bit 1 (LRDY1)
Bit 4/Local Bus Ready Control Bit 2 (LRDY2)
Bit 5/Local Bus Ready Control Bit 3 (LRDY3). MSB. These control bits determine the duration of the local bus
transaction in the PCI bridge mode. The bus transaction can either be controlled through the external LRDY input
signal or through a predetermined period of 1 to 11 LCLK periods.
0000 = use the LRDY signal input pin to control the bus transaction
0001 = bus transaction is defined as 1 LCLK period
0010 = bus transaction is defined as 2 LCLK periods
0011 = bus transaction is defined as 3 LCLK periods
0100 = bus transaction is defined as 4 LCLK periods
0101 = bus transaction is defined as 5 LCLK periods
0110 = bus transaction is defined as 6 LCLK periods
0111 = bus transaction is defined as 7 LCLK periods
1000 = bus transaction is defined as 8 LCLK periods
1001 = bus transaction is defined as 9 LCLK periods
1010 = bus transaction is defined as 10 LCLK periods
1011 = bus transaction is defined as 11 LCLK periods
1100 = illegal state
1101 = illegal state
1110 = illegal state
1111 = illegal state
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