- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97869 > DS3131 (MAXIM INTEGRATED PRODUCTS INC) SPECIALTY TELECOM CIRCUIT, PBGA256 PDF資料下載
參數(shù)資料
| 型號： | DS3131 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Telecom IC:Other |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 161/174頁 |
| 文件大小： | 1261K |
| 代理商： | DS3131 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁當前第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁
DS3131
87 of 174
9.2.4 Done Queue
The DMA writes to the receive done queue when it has filled a free data buffer with packet data and has
loaded the associated packet descriptor with all the necessary information. The descriptor location is
indicated through a 16-bit pointer that the host uses with the receive descriptor base address to find the
exact 32-bit address of the associated receive descriptor.
Figure 9-7. Receive Done-Queue Descriptor
dword 0
V
EOF
Status(3)
BUFCNT(3)
00b
HDLC CH#(6)
Descriptor Pointer (16)
Note:
The organization of the done queue is not affected by the enabling of Big Endian.
dword 0; Bits 0 to 15/Descriptor Pointer. This 16-bit value is the offset from the receive descriptor base
address of a receive packet descriptor that has been readied by the DMA and is available for the host to begin
processing.
dword 0; Bits 16 to 21/HDLC Channel Number. HDLC channel number, which can be from 1 to 40.
000000 (00h) = HDLC channel number 1
100111 (27h) = HDLC channel number 40
dword 0; Bits 22 to 23/Unused. Set to 0 by the DMA.
dword 0; Bits 24 to 26/Buffer Count (BUFCNT). If an HDLC channel has been configured to only write to
the done queue after a packet has been completely received (i.e., the threshold field in the receive DMA
configuration RAM is set to 000), then BUFCNT is always set to 000. If the HDLC channel has been
configured through the threshold field to write to the done queue after a programmable number of buffers
(from 1 to 7) has been filled, then BUFCNT corresponds to the number of buffers that have been written to
host memory. The BUFCNT is less than the threshold field value when the incoming packet does not require
the number of buffers specified in the threshold field.
000 = indicates that a complete packet has been received (only used when threshold = 000)
001 = 1 buffer has been filled
010 = 2 buffers have been filled
111 = 7 buffers have been filled
dword 0; Bits 27 to 29/Packet Status. These three bits report the final status of an incoming packet. They
are only valid when the EOF bit is set to 1 (EOF = 1).
000 = no error, valid packet received
001 = receive FIFO overflow (remainder of the packet discarded)
010 = CRC checksum error
011 = HDLC frame abort sequence detected (remainder of the packet discarded)
100 = nonaligned byte count error (not an integral number of bytes)
101 = long frame abort (max packet length exceeded; remainder of the packet discarded)
110 = PCI abort or parity data error (remainder of the packet discarded)
111 = reserved state (never occurs in normal device operation)
dword 0; Bit 30/End of Frame (EOF). This bit is set to 1 when this receive descriptor is the last one in the
current descriptor chain. This indicates that a packet has been fully received or an error has been detected,
which has caused a premature termination.
dword 0; Bit 31/Valid Done-Queue Descriptor (V). This bit is set to 0 by the receive DMA. Instead of
reading the receive done queue read pointer to locate completed done queue descriptors, the host can use this
bit since the DMA sets the bit to 0 when it is written into the queue. If the latter scheme is used, the host must
set this bit to 1 when the done queue descriptor is read.
相關PDF資料 |
PDF描述 |
|---|---|
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
| DS3150T | DATACOM, PCM TRANSCEIVER, PQFP48 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS3131DK | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS3134 | 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| DS-313PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號調節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
發(fā)布緊急采購，3分鐘左右您將得到回復。