參數(shù)資料
型號(hào)： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 117/174頁
文件大?。?/td> 1261K
代理商： DS3131
DS3131
47 of 174
6. LAYER 1
6.1 General Description
Each port on the DS3131 contains a dedicated bit-synchronous HDLC controller for that port. The Layer
1 block diagram in Figure 6-1 provides a block level description of the Layer 1 circuitry on each port.
Depending on the configuration, the DS3131 can have either 28 or 40 bit-synchronous HDLC interfaces
(Table 6-B). Figure 2-2 details the configurations shown in Table 6-B.
Each of the 40 ports can be independently configured into a different mode. The ports are capable of
operating at speeds up to 52MHz and are gapped clock tolerant. There are no restrictions on clock
gapping as long as the minimum clock period and high and low times listed in Section 13 are not
violated. Each port is a simple synchronous serial interface where data is clock into the device using the
RC input and clocked out of the device using the TC input. The transmit and receive timing is
completely independent. Each port has an associated receive port control register (RP[n]CR, where n = 0
to 39) and a transmit port control register (TP[n]CR, where n = 0 to 39). These control registers control
all of the circuitry in the Layer 1 block. See Section 6.2 for details.
HDLC Channel Assignment
HDLC channel numbers are assigned as shown in Table 6-A.
BERT Operation
The DS3131 contains an on-board full-featured BERT capable of generating and detecting both
pseudorandom and repeating serial bit patterns. The BERT function is a shared resource among the 40
ports on the DS3131 and can only be assigned to one port at a time. The details on the BERT are covered
in Section 6.3.
Table 6-A. HDLC Channel Assignment
PORT NUMBER
HDLC CHANNEL NUMBER
0
1
2
3
4
5
…
37
38
39
40
Table 6-B. Port Configuration Options
LOCAL BUS ENABLED?
NUMBER OF BIT-SYNCHRONOUS PORTS AVAILABLE
Yes
28
No
40
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