參數(shù)資料
型號(hào): DS3131
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Telecom IC:Other
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 67/174頁
文件大?。?/td> 1261K
代理商: DS3131
DS3131
159 of 174
12.3
Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register is connected between
JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one
stage toward the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR
state with JTMS high moves the controller to the Update-IR state. The falling edge of that same JTCLK
latches the data in the instruction shift register to the instruction parallel output. Table 12-A shows
instructions supported by the DS3131 and their respective operational binary codes.
Table 12-A. Instruction Codes
INSTRUCTION
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE/PRELOAD
Boundary Scan
010
BYPASS
Bypass
111
EXTEST
Boundary Scan
000
CLAMP
Boundary Scan
011
HIGHZ
Boundary Scan
100
IDCODE
Device Identification
001
SAMPLE/PRELOAD. SAMPLE/PRELOAD is a mandatory instruction for the IEEE 1149.1
specification that supports two functions. The digital I/Os of the DS3131 can be sampled at the boundary
scan register without interfering with the normal operation of the device by using the Capture-DR state.
SAMPLE/PRELOAD also allows the DS3131 to shift data into the boundary scan register through JTDI
using the Shift-DR state.
EXTEST. EXTEST allows testing of all interconnections to the DS3131. When the EXTEST instruction
is latched in the instruction register, the following actions occur. Once enabled through the Update-IR
state, the parallel outputs of all digital output pins are driven. The boundary scan register is connected
between JTDI and JTDO. The Capture-DR samples all digital inputs into the boundary scan register.
BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects
to JTDO through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without
affecting the device’s normal operation.
IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the
identification test register is selected. The device identification code loads into the identification register
on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially through JTDO. During Test-Logic-Reset, the identification code is forced
into the instruction register’s parallel output. The device ID code always has 1 in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by
16 bits for the device and 4 bits for the version. The device ID code for the DS3131 is 00008143h.
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