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參數(shù)資料
| 型號： | DS3131 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Telecom IC:Other |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 139/174頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | DS3131 |
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DS3131
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8.1.1 Receive High Watermark
The high watermark tells the device how many blocks should be written into the receive FIFO by the
HDLC controllers before the DMA begins sending the data to the PCI bus, or rather, how full the FIFO
should get before it should be emptied by the DMA. When the DMA begins reading the data from the
FIFO, it reads all available data and tries to completely empty the FIFO even if one or more EOFs (end
of frames) are detected. For example, if four blocks were link-listed together and the host programmed
the high watermark to three blocks, then the DMA would read the data out of the FIFO and transfer it to
the PCI bus after the HDLC controller had written three complete blocks in succession into the FIFO and
still had one block left to fill. The DMA would not read the data out of the FIFO again until another three
complete blocks had been written into the FIFO in succession by the HDLC controller or until an EOF
was detected. In this example of four blocks being link-listed together, the high watermark could also be
set to 1 or 2, but no other values would be allowed; the maximum value of the high watermark is the size
of the FIFO - 2. If an incoming packet does not fill the FIFO enough to reach the high watermark before
an EOF is detected, the DMA still requests that the data be sent to the PCI bus; it does not wait for
additional data to be written into the FIFO by the HDLC controllers.
8.1.2 Transmit Low Watermark
The low watermark tells the device how many blocks should be left in the FIFO before the DMA should
begin getting more data from the PCI bus, or rather, how empty the FIFO should get before it should be
filled again by the DMA. When the DMA begins reading the data from the PCI bus, it reads all available
data and tries to completely fill the FIFO even if one or more EOFs (HDLC packets) are detected. For
example, if five blocks were link-listed together and the host programmed the low watermark to two
blocks, then the DMA would read the data from the PCI bus and transfer it to the FIFO after the HDLC
controller has read three complete blocks in succession from the FIFO and, therefore, still had two
blocks left before the FIFO was empty. The DMA would not read the data from the PCI bus again until
another three complete blocks had been read from the FIFO in succession by the HDLC controllers. In
this example of five blocks being link-listed together, the low watermark could also be set to any value
from 1 to 4 (inclusive) but no other values would be allowed. When a new packet is written into a
completely empty FIFO by the DMA, the HDLC controllers wait until the FIFO fills beyond the low
watermark or until an EOF is seen before reading the data out of the FIFO.
相關(guān)PDF資料 |
PDF描述 |
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| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
| DS3150T | DATACOM, PCM TRANSCEIVER, PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3131DK | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS3134 | 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| DS-313PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
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