參數(shù)資料
型號： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 157/174頁
文件大?。?/td> 1261K
代理商： DS3131
DS3131
83 of 174
Empty Case
The receive free queue is considered empty when the read and write pointers are identical.
Receive Free-Queue Empty State
empty descriptor
read pointer >
empty descriptor
< write pointer
empty descriptor
Full Case
The receive free queue is considered full when the read pointer is ahead of the write pointer by one
descriptor. Therefore, one descriptor must always remain empty.
Receive Free-Queue Full State
valid descriptor
empty descriptor
< write pointer
read pointer >
valid descriptor
Table 9-D describes how to calculate the absolute 32-bit address of the read and write pointers for the
Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address
Calculation
BUFFER
ALGORITHM
Absolute Address = Free Queue Base + Write Pointer x 8
Large
Absolute Address = Free Queue Base + Read Pointer x 8
Absolute Address = Free Queue Base + Small Buffer Start x 8 + Write Pointer x 8
Small
Absolute Address = Free Queue Base + Small Buffer Start x 8 + Read Pointer x 8
Table 9-E. Receive Free-Queue Internal Address Storage
REGISTER
NAME
ADDRESS
Receive Free-Queue Base Address 0 (lower word)
RFQBA0
0700h
Receive Free-Queue Base Address 1 (upper word)
RFQBA1
0704h
Receive Free-Queue Large Buffer Host Write Pointer
RFQLBWP
0710h
Receive Free-Queue Large Buffer DMA Read Pointer
RFQLBRP
0718h
Receive Free-Queue Small Buffer Start Address
RFQSBSA
070Ch
Receive Free-Queue Small Buffer Host Write Pointer
RFQSBWP
0714h
Receive Free-Queue Small Buffer DMA Read Pointer
RFQSBRP
071Ch
Receive Free-Queue End Address
RFQEA
0708h
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