參數(shù)資料
型號： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 136/174頁
文件大?。?/td> 1261K
代理商： DS3131
DS3131
64 of 174
Bit 4/Transmit Invert Data Enable (TID). When this bit is set low, the outgoing HDLC packets are not inverted
after being generated. When this bit is set high, the HDLC controller inverts all the data (flags, information fields,
and FCS) after the packet has been generated.
0 = do not invert data
1 = invert all data (including flags and FCS)
Bit 5/Transmit Bit Flip (TBF). When this bit is set low, the HDLC controller obtains the first HDLC bit to be
transmitted from the lowest bit position of the PCI bus bytes (i.e., PAD[0], PAD[8], PAD[16], PAD[24]). When
this bit is set high, the HDLC controller obtains the first HDLC bit to be transmitted from the highest bit position
of the PCI bus bytes (i.e., PAD[7], PAD[15], PAD[23], PAD[31]).
0 = the first HDLC bit transmitted is obtained from the lowest bit position of the bytes on the PCI bus
1 = the first HDLC bit transmitted is obtained from the highest bit position of the bytes on the PCI bus
Bit 6/Transmit Corrupt FCS (TCFCS). When this bit is set low, the HDLC controller allows the frame
checksum sequence (FCS) to be transmitted as generated. When this bit is set high, the HDLC controller inverts all
the bits of the FCS before transmission occurs. This is useful in debugging and testing HDLC channels at the
system level.
0 = generate FCS normally
1 = invert all FCS bits
Bit 7/Transmit Abort Enable (TABTE). When this bit is set low, the HDLC controller performs normally, only
sending an abort sequence (eight 1s in a row) when an error occurs in the PCI block or the FIFO underflows.
When this bit is set high, the HDLC controller continuously transmits an all-ones pattern (i.e., an abort sequence).
This bit is still active when the HDLC controller is configured in the transparent mode (TTRANS = 1).
0 = normal generation of abort
1 = constant abort generated
Bits 8 to 11/Transmit Flag Generation Bits 0 to 3 (TFG0/TFG1/TFG2/TFG3). These four bits determine how
many flags and interfill bytes are sent in between consecutive packets.
TFG3
TFG2
TFG1
TFG0
ACTION
0
Share closing and opening flag
0
1
Closing flag/no interfill bytes/opening flag
0
1
0
Closing flag/1 interfill byte/opening flag
0
1
Closing flag/2 interfill bytes/opening flag
0
1
0
Closing flag/3 interfill bytes/opening flag
0
1
0
1
Closing flag/4 interfill bytes/opening flag
0
1
0
Closing flag/5 interfill bytes/opening flag
0
1
Closing flag/6 interfill bytes/opening flag
1
0
Closing flag/7 interfill bytes/opening flag
1
0
1
Closing flag/8 interfill bytes/opening flag
1
0
1
0
Closing flag/9 interfill bytes/opening flag
1
0
1
Closing flag/10 interfill bytes/opening flag
1
0
Closing flag/11 interfill bytes/opening flag
1
0
1
Closing flag/12 interfill bytes/opening flag
1
0
Closing flag/13 interfill bytes/opening flag
1
Closing flag/14 interfill bytes/opening flag
Bit 12/Transmit Zero Stuffing Disable (TZSD). When this bit is set low, the HDLC controller performs zero
stuffing on the outgoing data stream. When this bit is set high, the outgoing data stream is not zero stuffed. This
bit is ignored when the HDLC controller is configured in the transparent mode (TTRANS = 1).
0 = zero stuffing enabled
1 = zero stuffing disabled
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