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參數(shù)資料
| 型號(hào)： | DS3131 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Telecom IC:Other |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 41/174頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | DS3131 |
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DS3131
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10.2.4
Status Bits (PCMD1)
The upper words in the PCMD1 register are the status portion, which report events as they occur. As mentioned
earlier, reads of the status portion occur normally, but writes are unique in that bits can only be reset (i.e., forced to
0). This occurs when 1 is written to a bit position. Writes with a 0 to a bit position have no affect. This allows
individual bits to be reset.
Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device.
Bit 21/66MHz Capable (66MHz). This read-only bit is forced to 0 by the device to indicate that it is not capable
of running at 66MHz.
Bit 22/User-Definable Features Capable (UDF). This read-only bit is forced to 0 by the device to indicate that it
does not support user-definable features.
Bit 23/Fast Back-to-Back Capable Target (FBBCT). This read-only bit is forced to 1 by the device to indicate
that it is capable of accepting fast back-to-back transactions when the transactions are not from the same agent.
Bit 24/PCI Parity Error Reported (PARR). This read-only bit is forced to 0 by the device since the device
cannot act as a bus master.
Bits 25, 26/Device Timing Select Bits 0 and 1 (DTS0 and DTS1). These read-only bits are forced to 01b by the
device to indicate that they are capable of the medium timing requirements for the PDEVSEL signal.
Bit 27/Target Abort Initiated (TABT). This read/write bit is set to 1 when the device terminates a bus
transaction with a target abort. This occurs only when the local bus is operating in the bus arbitration mode and the
local bus does not have bus control when the host requests access. This bit can be reset (set to 0) by the host by
writing 1 to this bit.
Bit 28/Target Abort Detected by Master (TABTM). This read-only bit is forced to 0 by the device since the
device cannot act as a bus master.
Bit 29/Master Abort (MABT). This read-only bit is forced to 0 by the device since the device cannot act as a bus
master.
Bit 30/PCI System Error Reported (PSE). This read/write bit is set to 1 when the device asserts the PSERR
signal (even if it is disabled through the PSEC command bit). This bit can be reset (set to 0) by the host by writing
1 to this bit.
Bit 31/PCI Parity Error Reported (PPE). This read/write bit is set to 1 when the device detects a parity error
(even if parity is disabled through the PARC command bit). This bit can be reset (set to 0) by the host by writing 1
to this bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
| DS3150T | DATACOM, PCM TRANSCEIVER, PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3131DK | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS3134 | 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| DS-313PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
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