- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97869 > DS3131 (MAXIM INTEGRATED PRODUCTS INC) SPECIALTY TELECOM CIRCUIT, PBGA256 PDF資料下載
參數(shù)資料
| 型號(hào)： | DS3131 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Telecom IC:Other |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 36/174頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | DS3131 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁
DS3131
130 of 174
10.2.2
Status Bits (PCMD0)
The upper words in the PCMD0 register are the status portion, which report events as they occur. As previously
mentioned, reads of the status portion occur normally but writes are unique in that bits can only be reset (i.e.,
forced to 0). This occurs when 1 is written to a bit position. Writes with a 0 to a bit position have no affect. This
allows individual bits to be reset.
Bits 16 to 20/Reserved. These read-only bits are forced to 0 by the device.
Bit 21/66MHz Capable (66MHz). This read-only bit is forced to 0 by the device to indicate that it is not capable
of running at 66MHz.
Bit 22/User-Definable Features Capable (UDF). This read-only bit is forced to 0 by the device to indicate that it
does not support user-definable features.
Bit 23/Fast Back-to-Back Capable Target (FBBCT). This read-only bit is forced to 1 by the device to indicate
that it is capable of accepting fast back-to-back transactions when the transactions are not from the same agent.
Bit 24/PCI Parity Error Reported (PARR). This read/write bit is set to 1 when the device is a bus master and
detects or asserts the PPERR signal when the PARC command bit is enabled. This bit can be reset (set to 0) by the
host by writing 1 to this bit.
0 = no parity errors have been detected
1 = parity errors detected
Bits 25, 26/Device Timing Select Bits 0 and 1 (DTS0 and DTS1). These read-only bits are forced to 01b by the
device to indicate that it is capable of the medium timing requirements for the PDEVSEL signal.
Bit 27/Target Abort Initiated (TABT). This read-only bit is forced to 0 by the device since it does not terminate
a bus transaction with a target abort when the device is a target.
Bit 28/Target Abort Detected by Master (TABTM). This read/write bit is set to 1 when the device is a bus
master and it detects that a bus transaction has been aborted by the target with a target abort. This bit can be reset
(set to 0) by the host by writing 1 to this bit.
Bit 29/Master Abort (MABT). This read/write bit is set to 1 when the device is a bus master and the bus
transaction is terminated with a master abort (except for special cycle). This bit can be reset (set to 0) by the host
by writing 1 to this bit.
Bit 30/PCI System Error Reported (PSE). This read/write bit is set to 1 when the device asserts the PSERR
signal (even if it is disabled through the PSEC command bit). This bit can be reset (set to 0) by the host by writing
1 to this bit.
Bit 31/PCI Parity Error Reported (PPE). This read/write bit is set to 1 when the device detects a parity error
(even if parity is disabled through the PARC command bit). This bit can be reset (set to 0) by the host by writing 1
to this bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
| DS3150T | DATACOM, PCM TRANSCEIVER, PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3131DK | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS3134 | 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| DS-313PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。