參數(shù)資料
型號： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 20/174頁
文件大?。?/td> 1261K
代理商： DS3131
DS3131
116 of 174
9.3.5 DMA Configuration RAM
The device contains an on-board set of 240 dwords (6 dwords per channel times 40 channels) that are
used by the host to configure the DMA and used by the DMA to store values locally when it is
processing a packet. Most of the fields within the DMA configuration RAM are for DMA use and the
host never writes to these fields. The host is only allowed to write (configure) to the lower word of
dword 1 for each HDLC channel. In Figure 9-21, the host-configurable fields are denoted with a thick
box.
Figure 9-21. Transmit DMA Configuration RAM
MSB
31
LSB
0
Transmit DMA Configuration RAM
Fields shown within the thick box
are written by the host; all other
fields are for DMA use and can
only be read by the host.
Next Descriptor Pointer (16)
Next Priority Pending Descriptor Pointer (16)
Byte Count (13)
Current Packet Data Buffer Address (32)
Start Descriptor Pointer (16)
CH
EN
Last Pending Descriptor Pointer (16)
Next Pending Descriptor Pointer (16)
Next Priority Descriptor Pointer (16)
Last Priority Pending Descriptor Pointer (16)
DQS
unused (16)
EOF CV
PEND
ST(2)
PRI
ST(2)
unused (9)
PPP
un-
used
Next Descriptor Pointer (16)
Next Priority Pending Descriptor Pointer (16)
Byte Count (13)
Current Packet Data Buffer Address (32)
Start Descriptor Pointer (16)
CH
EN
Last Pending Descriptor Pointer (16)
Next Pending Descriptor Pointer (16)
Next Priority Descriptor Pointer (16)
Last Priority Pending Descriptor Pointer (16)
DQS
unused (16)
EOF CV
PEND
ST(2)
PRI
ST(2)
unused (9)
PPP
un-
used
dword 0
dword 1
dword 2
HDLC
CH 40
dword 3
dword 4
dword 5
dword 0
dword 1
dword 2
HDLC
CH 1
dword 3
dword 4
dword 5
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