參數(shù)資料
型號: DS3131
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Telecom IC:Other
英文描述: SPECIALTY TELECOM CIRCUIT, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 69/174頁
文件大?。?/td> 1261K
代理商: DS3131
DS3131
160 of 174
12.4
Test Registers
IEEE 1149.1 requires a minimum of two test registers, the bypass register and the boundary scan
register. An optional identification register has been included in the DS3131 design that is used in
conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
Bypass Register
This is a single 1-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions that provides a short path between JTDI and JTDO.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells. Visit www.maxim-ic.com/telecom for a downloadable BDSL file that contains all bit
identity and definition information.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This
register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-
Reset state.
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