參數(shù)資料
型號(hào)： DS3131
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁(yè)數(shù)： 91/174頁(yè)
文件大?。?/td> 1261K
代理商： DS3131
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DS3131
23 of 174
Signal Name:
LBHE
Signal Description:
Local Bus Byte-High Enable (PCI Bridge Mode Only)
Signal Type:
Output (three-state capable)
This active-low output signal is asserted when all 16 bits of the data bus (LD[15:0]) are active. It remains high if
only the lower 8 bits (LD[7:0)] are active. If bus arbitration is enabled through the LARBE control bit in the
LBBMC register, this signal is three-stated when the local bus is not currently involved in a bus transaction and
driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. This signal
remains in three-state when the local bus is not involved in a bus transaction and is in configuration mode
(LMS = 1).
Signal Name:
LCLK
Signal Description:
Local Bus Clock (PCI Bridge Mode Only)
Signal Type:
Output (three-state capable)
This signal outputs a buffered version of the clock applied at the PCLK input. All local bus signals are generated
and sampled from this clock. This output is three-stated when the local bus is in configuration mode (LMS = 1). It
can be disabled in the PCI bridge mode through the LBBMC register.
Signal Name:
LCS
Signal Description:
Local Bus Chip Select (Configuration Mode Only)
Signal Type:
Input
This active-low signal must be asserted for the device to accept a read or write command from an external host.
This signal is ignored in the PCI bridge mode (LMS = 0) and should be connected high.
3.4 JTAG Signal Description
Signal Name:
JTCLK
Signal Description:
JTAG IEEE 1149.1 Test Serial Clock
Signal Type:
Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, this
signal should be pulled high.
Signal Name:
JTDI
Signal Description:
JTAG IEEE 1149.1 Test Serial-Data Input
Signal Type:
Input (with internal 10k pullup)
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this signal should
be pulled high. This signal has an internal pullup.
Signal Name:
JTDO
Signal Description:
JTAG IEEE 1149.1 Test Serial-Data Output
Signal Type:
Output
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this signal should be left
open circuited.
Signal Name:
JTRST
Signal Description:
JTAG IEEE 1149.1 Test Reset
Signal Type:
Input (with internal 10k pullup)
This signal is used to synchronously reset the test access port controller. At power-up, JTRST must be set low and
then high. This action sets the device into the boundary scan bypass mode, allowing normal device operation. If
boundary scan is not used, this signal should be held low. This signal has an internal pullup.
Signal Name:
JTMS
Signal Description:
JTAG IEEE 1149.1 Test Mode Select
Signal Type:
Input (with internal 10k pullup)
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE
1149.1 states. If not used, this signal should be pulled high. This signal has an internal pullup.
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DS3134 DATACOM, FRAMER, PBGA256
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參數(shù)描述
DS3131DK 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube
DS3134 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
DS-313PIN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous
DS-313-PIN 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel
DS31400 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter
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