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參數(shù)資料
| 型號(hào)： | DS3131 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Telecom IC:Other |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 150/174頁(yè) |
| 文件大小： | 1261K |
| 代理商： | DS3131 |
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DS3131
77 of 174
On an HDLC channel basis in the receive DMA configuration RAM, the host instructs the DMA how to
use the large and small buffers for the incoming packet data on that particular HDLC channel. The host
has three options: (1) only use large buffers, (2) only use small buffers, or (3) first fill a small buffer,
then if the incoming packet requires more buffer space, use one or more large buffers for the remainder
of the packet. The host selects the option through the size field in the receive configuration RAM
(Section 9.2.5). Large buffers are best used for data-intensive, time-insensitive packets like graphics
files, whereas small buffers are best used for time-sensitive information like real-time voice.
Table 9-B. Receive DMA Main Operational Areas
DESCRIPTORS
FUNCTION
SECTION
Packet
A dedicated area of memory that describes the location and attributes of
the packet data.
9.2.2
Free Queue
A dedicated area of memory that the host writes to inform the DMA
where to store incoming packet data.
9.2.3
Done Queue
A dedicated area of memory that the DMA writes to inform the host
that the packet data is ready for processing.
9.2.4
The done-queue descriptors contain information that the DMA wishes to pass to the host. Through the
done-queue descriptors, the DMA informs the host about the incoming packet data and where to find the
packet descriptors that it has written into main memory. Each completed descriptor contains the starting
address of the data buffer where the packet data is stored.
If enabled, the DMA can burst read the free-queue descriptors and burst write the done-queue
descriptors. This helps minimize PCI bus accesses, freeing the PCI bus up to do more time critical
functions. See Sections 9.2.3 and 9.2.4 for more details about this feature.
Receive DMA Actions
A typical scenario for the receive DMA is as follows:
1) The receive DMA gets a request from the receive FIFO that it has packet data that needs to be sent to
the PCI bus.
2) The receive DMA determines whether the incoming packet data should be stored in a large buffer or
a small buffer.
3) The receive DMA then reads a free-queue descriptor (either by reading a single descriptor or a burst
of descriptors), indicating where, in main memory, there exists some free data buffer space and
where the associated free packet descriptor resides.
4) The receive DMA starts storing packet data in the previously free buffer data space by writing it out
through the PCI bus.
5) When the receive DMA realizes that the current data buffer is filled (by knowing the buffer size it
can calculate this), it then reads another free-queue descriptor to find another free data buffer and
packet descriptor location.
6) The receive DMA then writes the previous packet descriptor and creates a linked list by placing the
current descriptor in the next descriptor pointer field; it then starts filling the new buffer location.
Figure 9-1 provides an example of packet descriptors being link listed together (see Channel 2).
7) This continues to the entire packet data is stored.
8) The receive DMA either waits until a packet has been completely received or until a programmable
number (from 1 to 7) of data buffers have been filled before writing the done-queue descriptor, which
indicates to the host that packet data is ready for processing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
| DS3150T | DATACOM, PCM TRANSCEIVER, PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3131DK | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS3134 | 功能描述:IC CTRLR HDLC CHATEAU 256-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| DS-313PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
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