型號(hào) | 廠商 | 描述 |
cy7c1006 2 3 4 5 6 7 8 |
Cypress Semiconductor Corp. | 256K x 4 Static RAM(256K x4 靜態(tài) RAM) |
cy7c1146v18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
Cypress Semiconductor Corp. | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1150v18-333bzxc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1150v18-333bzxi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1150v18-375bzc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1150v18-375bzi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1150v18-375bzxc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1150v18-375bzxi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1146v18-333bzc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1146v18-333bzi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1146v18-333bzxc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1146v18-333bzxi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1146v18-375bzc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1146v18-375bzi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1146v18-375bzxc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1146v18-375bzxi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1148v18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
Cypress Semiconductor Corp. | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1148v18-333bzc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1148v18-333bzi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1148v18-333bzxc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1148v18-333bzxi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1148v18-375bzc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1148v18-375bzi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1148v18-375bzxc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1148v18-375bzxi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1150v18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
Cypress Semiconductor Corp. | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1150v18-333bzc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1150v18-333bzi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1156v18-300bzxi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1141v18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
Cypress Semiconductor Corp. | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1141v18-300bzc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1141v18-300bzi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1141v18-300bzxc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1141v18-300bzxi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1143v18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
Cypress Semiconductor Corp. | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1143v18-300bzc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1143v18-300bzi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1143v18-300bzxc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1143v18-300bzxi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1145v18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
Cypress Semiconductor Corp. | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1145v18-300bzc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1145v18-300bzi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1145v18-300bzxc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1145v18-300bzxi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1156v18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
Cypress Semiconductor Corp. | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1156v18-300bzc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1156v18-300bzi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1156v18-300bzxc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
CYPRESS SEMICONDUCTOR CORP | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
cy7c1223f-133ac 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
CYPRESS SEMICONDUCTOR CORP | 2-Mb (128K x 18) Pipelined DCD Sync SRAM |
cy7c1223f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 |
Cypress Semiconductor Corp. | 2-Mb (128K x 18) Pipelined DCD Sync SRAM |