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參數(shù)資料
| 型號： | CY7C1141V18-300BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 2M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 954K |
| 代理商： | CY7C1141V18-300BZXC |
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18-Mbit QDR-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
CY7C1141V18
CY7C1156V18
CY7C1143V18
CY7C1145V18
Cypress Semiconductor Corporation
Document Number: 001-06583 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 15, 2007
Features
■
Separate Independent read and write data ports
Supports concurrent transactions
■
300 MHz to 375 MHz clock for high bandwidth
■
4-Word Burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 750 MHz) at 375 MHz
■
Read latency of 2.0 clock cycles
■
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■
Single multiplexed address input bus latches address inputs
for both read and write ports
■
Separate Port Selects for depth expansion
■
Data valid pin (QVLD) to indicate valid data on the output
■
Synchronous internally self-timed writes
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency providing most current data
■
Core V
DD
= 1.8V ± 0.1V; IO V
DDQ
= 1.4V to V
DD[1]
■
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
Variable drive HSTL output buffers
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1141V18 – 2M x 8
CY7C1156V18 – 2M x 9
CY7C1143V18 – 1M x 18
CY7C1145V18 – 512K x 36
Functional Description
The CY7C1141V18, CY7C1156V18, CY7C1143V18, and
CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II+ architecture. QDR-II+ architecture
consists of two separate ports to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common IO devices. Access to each
port is accomplished through a common address bus.
Addresses for read and write addresses are latched on alternate
rising edges of the input (K) clock. Accesses to the QDR-II+ read
and write ports are completely independent of one another. To
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1141V18), or 9-bit words (CY7C1156V18), or 18-bit words
(CY7C1143V18), or 36-bit words (CY7C1145V18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks K and K, memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each port.
Port Selects enable each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
375 MHz
333 MHz
300 MHz
Unit
Maximum Operating Frequency
375
333
300
MHz
Maximum Operating Current
1020
920
850
mA
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V
DDQ
= 1.4V to V
DD
.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1141V18-300BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1143V18 | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1143V18-300BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1143V18-300BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1143V18-300BZXC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1143KV18-400BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18MB (1Mx18) 1.8v 400MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1143KV18-400BZI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18MB (1Mx18) 1.8v 400MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1143KV18-450BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18MB (1Mx18) 1.8v 450MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1145KV18-400BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18MB (512Kx36) 1.8v 400MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1145KV18-400BZXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb 1.8V 512Kb x 36 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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