參數(shù)資料
型號(hào): CY7C1146V18
廠商: Cypress Semiconductor Corp.
英文描述: 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
中文描述: 18兆位的DDR - II SRAM的2字突發(fā)架構(gòu)(2.0周期讀寫(xiě)延遲)
文件頁(yè)數(shù): 7/27頁(yè)
文件大小: 969K
代理商: CY7C1146V18
CY7C1146V18
CY7C1157V18
CY7C1148V18
CY7C1150V18
Document Number: 001-06621 Rev. *C
Page 7 of 27
DOFF
Input
DLL Turn Off
Active LOW
. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operation are different from those listed in this data sheet. For normal
operation, connect this pin to a pull up through a 10 K
or less pull up resistor. The device behaves
in DDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to
167 MHz with DDR-I timing.
TDO
Output
TDO for JTAG
.
TCK
Input
TCK pin for JTAG
.
TDI
Input
TDI pin for JTAG
.
TMS
Input
TMS pin for JTAG
.
NC
N/A
Not connected to the die
. Tie to any voltage level.
NC/36M
N/A
Not connected to the die
. Tie to any voltage level.
NC/72M
N/A
Not connected to the die
. Tie to any voltage level.
NC/144M
N/A
Not connected to the die
. Tie to any voltage level.
NC/288M
N/A
Not connected to the die
. Tie to any voltage level.
V
REF
Input-
Reference
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs, Outputs, and
AC measurement points.
V
DD
Power Supply
Power supply inputs to the core of the device
.
V
SS
Ground
Ground for the device
.
V
DDQ
Power Supply
Power supply inputs for the outputs of the device
.
Pin Definitions
(continued)
Pin Name
IO
Pin Description
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1150V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-375BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-375BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-375BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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