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參數(shù)資料
| 型號： | CY7C1223F |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2-Mb (128K x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 2 MB的（128K的× 18）流水線雙氰胺同步靜態(tài)存儲器 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 328K |
| 代理商： | CY7C1223F |
CY7C1223F
Document #: 38-05418 Rev. *A
Page 4 of 15
Pin Descriptions
Pin
TQFP
Type
Input-
Description
A0, A
1
, A
37,36,32,33
34,35,44,45,
46,47,48,49,
80,81,82,99,
100
93,94
Synchronous
Address Inputs used to select one of the 128K address locations
. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3
are sampled active. A
[1:0]
are fed to the two-bit counter.
BW
[A:B]
Input-
Synchronous
Input-
Synchronous
Byte Write Select Inputs, active LOW
. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW
. When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW
[A:B]
and BWE).
Byte Write Enable Input, active LOW
. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input
. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and
CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW
. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW
. When
asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active
LOW
. When asserted LOW, addresses presented to the device are captured in the
address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is
deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active
LOW
. When asserted LOW, addresses presented to the device are captured in the
address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input, active HIGH
. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal opera-
tion, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP
[A:B]
are
placed in a three-state condition.
Power Supply
Power supply inputs to the core of the device
.
Ground
Ground for the core of the device
.
I/O Power
Supply
I/O Ground
Ground for the I/O circuitry
.
GW
88
BWE
87
Input-
Synchronous
Input-
Clock
Input-
Synchronous
CLK
89
CE
1
98
CE
2
97
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CE
3
92
OE
86
ADV
83
Input-
Synchronous
Input-
Synchronous
ADSP
84
ADSC
85
Input-
Synchronous
ZZ
64
Input-
Asynchronous
DQs
DQP
[A:B]
8,9,12,13,
18,19,22,
23,24,58,
59,62,63,
68,69,72,
73,74
15,41,65, 91
17,40,67,90
4,11,20,27,
54,61,70,77
5,10,21,26,
55,60,71,76
31
I/O-
Synchronous
V
DD
V
SS
V
DDQ
Power supply for the I/O circuitry
.
V
SSQ
MODE
Input-
Static
Selects Burst Order
. When tied to GND selects linear burst sequence. When tied
to V
DD
or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
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