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參數(shù)資料
| 型號(hào)： | CY7C1223F |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2-Mb (128K x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 2 MB的（128K的× 18）流水線雙氰胺同步靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 9/15頁(yè) |
| 文件大?。?/td> | 328K |
| 代理商： | CY7C1223F |
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CY7C1223F
Document #: 38-05418 Rev. *A
Page 9 of 15
Capacitance
[9]
Parameter
Description
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 3.3V
V
DDQ
= 3.3V
Max.
5
5
5
Unit
pF
pF
pF
C
IN
C
CLK
C
I/O
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[14, 15]
Parameter
Description
166 MHz
133 MHz
Unit
Min.
Max.
Min.
Max.
t
POWER
Clock
V
DD
(Typical) to the first Access
[10]
1
1
ms
t
CYC
t
CH
t
CL
Output Times
Clock Cycle Time
6.0
7.5
ns
Clock HIGH
2.5
3.0
ns
Clock LOW
2.5
3.0
ns
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
Data Output Valid After CLK Rise
3.5
4.0
ns
Data Output Hold After CLK Rise
Clock to Low-Z
[11, 12, 13]
Clock to High-Z
[11, 12, 13]
2.0
2.0
ns
0
0
ns
3.5
4.0
ns
OE LOW to Output Valid
OE LOW to Output Low-Z
[11, 12, 13]
OE HIGH to Output High-Z
[11, 12, 13]
3.5
4.5
ns
0
0
ns
3.5
4.0
ns
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Address Set-up Before CLK Rise
1.5
1.5
ns
ADSC, ADSP Set-up Before CLK Rise
1.5
1.5
ns
ADV Set-up Before CLK Rise
1.5
1.5
ns
GW, BWE, BW
[A:B]
Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
1.5
1.5
ns
1.5
1.5
ns
Chip Enable Set-up Before CLK Rise
1.5
1.5
ns
Notes:
10.This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
11. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13.This parameter is sampled and not 100% tested.
14.Timing reference level is 1.5V when V
= 3.3V.
15.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
OUTPUT
R = 317
R = 351
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
T
= 1.5V
3.3V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤
1 ns
≤
1 ns
(c)
3.3V I/O Test Load
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