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參數(shù)資料
| 型號： | CY7C1223F |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2-Mb (128K x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 2 MB的（128K的× 18）流水線雙氰胺同步靜態(tài)存儲器 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大小： | 328K |
| 代理商： | CY7C1223F |
CY7C1223F
Document #: 38-05418 Rev. *A
Page 8 of 15
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................... –65°C to +150°
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +4.6V
DC Voltage Applied to Outputs
in three-state ....................................... –0.5V to V
DDQ
+0.5V
DC Input Voltage......................................–0.5V to V
DD
+0.5V
Electrical Characteristics
Over the Operating Range
[7, 8]
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883,Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range
Com’l
Ambient
Temperature (T
A
)
0°C to +70°C
V
DD
V
DDQ
3.3V
5%/+10%
3.3V
5% to
V
DD
Parameter
V
DD
V
DDQ
V
OH
V
OL
V
IH
Description
Test Conditions
Min.
3.135
3.135
2.4
Max.
3.6
V
DD
Unit
V
V
V
V
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
[7]
V
DDQ
= 3.3V, V
DD
= Min., I
OH
= –4.0 mA
V
DDQ
= 3.3V, V
DD
= Min., I
OL
= 8.0 mA
V
DDQ
= 3.3V
0.4
V
DD
+
0.3V
0.8
5
2.0
V
IL
I
X
Input LOW Voltage
[7]
Input Load Current except ZZ
and MODE
Input Current of MODE
V
DDQ
= 3.3V
GND
≤
V
I
≤
V
DDQ
–0.3
–5
V
μ
A
Input = V
SS
Input = V
DD
Input = V
SS
Input = V
DD
GND
≤
V
I
≤
V
DDQ,
Output Disabled
–30
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
mA
5
Input Current of ZZ
–5
30
5
240
225
100
90
I
OZ
I
DD
Output Leakage Current
V
DD
Operating Supply Current V
DD
= Max., I
OUT
= 0 mA,
–5
f = f
MAX
= 1/t
CYC
6-ns cycle, 166 MHz
7.5-ns cycle,133MHz
6-ns cycle, 166 MHz
7.5-ns cycle,133MHz
I
SB1
Automatic CS
Power-down
Current—TTL Inputs
Automatic CS
Power-down
Current—CMOS Inputs
Automatic CS
Power-down
Current—CMOS Inputs
V
DD
= Max., Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
,
f = f
MAX
= 1/t
CYC
V
DD
= Max., Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DDQ
– 0.3V,
f = 0
V
DD
= Max., Device Deselected,
or V
IN
≤
0.3V or
V
IN
> V
DDQ
– 0.3V,
f = f
MAX
= 1/t
CYC
V
DD
= Max., Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = 0
I
SB2
All speeds
40
mA
I
SB3
6.0-ns cycle, 166 MHz
7.5-ns cycle, 133MHz
85
75
mA
mA
I
SB4
Automatic CS Power-down
Current—TTL Inputs
All speeds
45
mA
Thermal Characteristics
[9]
Parameter
Θ
JA
Description
Test Conditions
TQFP
Package
41.83
Unit
°C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to case)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
Θ
JC
9.99
°C/W
Notes:
7. Overshoot: V
(AC) < V
+1.5V (Pulse width less than t
/2), undershoot: V
(AC)> –2V (Pulse width less than t
CYC
/2).
8. Power-up: Assumes a linear ramp from 0V to V
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
9. Tested initially and after any design or process change that may affect these parameters.
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