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參數(shù)資料
| 型號(hào)： | CY7C1156V18-300BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 2M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 954K |
| 代理商： | CY7C1156V18-300BZC |
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CY7C1141V18
CY7C1156V18
CY7C1143V18
CY7C1145V18
Document Number: 001-06583 Rev. *C
Page 7 of 28
CQ
Echo Clock
Synchronous Echo Clock Outputs
. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in the
“Switching Characteristics”
on page 23.
ZQ
Input
Output Impedance Matching Input
. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, connect this pin directly to V
DDQ
, which enables
the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off
Active LOW
. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operationis different from those listed in this data sheet. For normal
operation, connect this pin to a pull up through a 10 K
or less pull up resistor. The device behaves
in QDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to
167 MHz with QDR-I timing.
TDO
Output
TDO for JTAG
.
TCK
Input
TCK pin for JTAG
.
TDI
Input
TDI pin for JTAG
.
TMS
Input
TMS pin for JTAG
.
NC
N/A
Not connected to the die
. Tie to any voltage level.
NC/36M
N/A
Not connected to the die
. Tie to any voltage level.
NC/72M
N/A
Not connected to the die
. Tie to any voltage level.
NC
/144M
N/A
Not connected to the die
. Tie to any voltage level.
NC
/288M
N/A
Not connected to the die
. Tie to any voltage level.
V
REF
Input-
Reference
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs, outputs, and
AC measurement points.
V
DD
Power Supply
Power supply inputs to the core of the device
.
V
SS
Ground
Ground for the device
.
V
DDQ
Power Supply
Power supply inputs for the outputs of the device
.
Pin Definitions
(continued)
Pin Name
IO
Pin Description
[+] Feedback
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