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參數(shù)資料
| 型號(hào)： | CY7C1141V18-300BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 2M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大小： | 954K |
| 代理商： | CY7C1141V18-300BZC |
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CY7C1141V18
CY7C1156V18
CY7C1143V18
CY7C1145V18
Document Number: 001-06583 Rev. *C
Page 12 of 28
The write cycle descriptions of
CY7C1145V18 follows.
[2, 10]
BWS
0
BWS
1
BWS
2
BWS
3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D
[35:0]
) are written into
the device.
L
L
L
L
–
L–H During the data portion of a write sequence, all four bytes (D
[35:0]
) are written into
the device.
L
H
H
H
L–H
–
During the data portion of a write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
remains unaltered.
L
H
H
H
–
L–H During the data portion of a write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
remains unaltered.
H
L
H
H
L–H
–
During the data portion of a write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
remains unaltered.
H
L
H
H
–
L–H During the data portion of a write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
remains unaltered.
H
H
L
H
L–H
–
During the data portion of a write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
remains unaltered.
H
H
L
H
–
L–H During the data portion of a write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
remains unaltered.
H
H
H
L
L–H
–
During the data portion of a write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
remains unaltered.
H
H
H
L
–
L–H During the data portion of a write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
remains unaltered.
H
H
H
H
L–H
–
No data is written into the device during this portion of a write operation.
H
H
H
H
–
L–H No data is written into the device during this portion of a write operation.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1141V18-300BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1141V18-300BZXC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1141V18-300BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1143V18 | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1143V18-300BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
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| CY7C1143KV18-400BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18MB (1Mx18) 1.8v 400MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1143KV18-400BZI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18MB (1Mx18) 1.8v 400MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1143KV18-450BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18MB (1Mx18) 1.8v 450MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1145KV18-400BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18MB (512Kx36) 1.8v 400MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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