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參數資料
| 型號： | CY7C1141V18-300BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 2M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165 |
| 文件頁數： | 9/28頁 |
| 文件大小： | 954K |
| 代理商： | CY7C1141V18-300BZC |
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CY7C1141V18
CY7C1156V18
CY7C1143V18
CY7C1145V18
Document Number: 001-06583 Rev. *C
Page 9 of 28
Depth Expansion
The CY7C1143V18 has a Port Select input for each port. This
enables easy depth expansion. Both Port Selects are sampled
on the rising edge of the Positive Input Clock only (K). Each
port select input can deselect the specified port. Deselecting
a port does not affect the other port. All pending transactions
(read and write) are completed before the device is
deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
SS
to enable the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175
and 350
,
with
V
DDQ
= 1.5V. The output impedance is adjusted every 1024
cycles upon power up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data
capture on high speed systems. Two echo clocks are
generated by the QDR-II+. CQ is referenced with respect to K
and CQ is referenced with respect to K. These are free running
clocks and are synchronized to the input
clock of the QDR-II+.
The timings for the echo clocks are shown in the AC timing
table.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR-II+ to simplify data capture on
high speed systems. The QVLD is generated by the QDR-II+
device along with data output. This signal is also edge-aligned
with the echo clock and follows the timing of any data pin. This
signal is asserted half a cycle before valid data arrives.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. When the DLL is turned off, the device behaves in
QDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL
Considerations in QDRII/DDRII/QDRII+/DDRII+”. The DLL
can also be reset by slowing or stopping the input clocks K and
K for a minimum of 30 ns. However, it is not necessary for the
DLL to be reset to lock to the desired frequency. During power
up, when the DOFF is tied HIGH, the DLL gets locked after
2048 cycles of stable clock.
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1141V18-300BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1141V18-300BZXC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1141V18-300BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1143V18 | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1143V18-300BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1143KV18-400BZC | 功能描述:靜態(tài)隨機存取存儲器 18MB (1Mx18) 1.8v 400MHz DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1143KV18-400BZI | 功能描述:靜態(tài)隨機存取存儲器 18MB (1Mx18) 1.8v 400MHz DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1143KV18-450BZC | 功能描述:靜態(tài)隨機存取存儲器 18MB (1Mx18) 1.8v 450MHz DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1145KV18-400BZXC | 功能描述:靜態(tài)隨機存取存儲器 18MB (512Kx36) 1.8v 400MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1145KV18-400BZXCT | 功能描述:靜態(tài)隨機存取存儲器 18Mb 1.8V 512Kb x 36 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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