參數(shù)資料
型號: CY7C1006
廠商: Cypress Semiconductor Corp.
英文描述: 256K x 4 Static RAM(256K x4 靜態(tài) RAM)
中文描述: 256K × 4靜態(tài)存儲器(256K x4靜態(tài)內(nèi)存)
文件頁數(shù): 5/8頁
文件大?。?/td> 203K
代理商: CY7C1006
CY7C106
CY7C1006
5
Data Retention Characteristics
Over the Operating Range (L Version Only)
Parameter
V
DR
I
CCDR
t
CDR[4]
t
R[4]
Description
Conditions
[10]
Min.
2.0
Max.
Unit
V
μ
A
ns
V
CC
for Data Retention
Data Retention Current
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
50
Chip Deselect to Data Retention Time
0
Operation Recovery Time
t
RC
ns
Data Retention Waveform
4.5V
4.5V
CE
V
CC
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
C106–5
Switching Waveforms
Read Cycle No.1
[11, 12]
Read Cycle No. 2 (OE Controlled)
[12, 13]
Notes:
10. No input may exceed V
+0.5V.
11. Device is continuously selected, OE and CE = V
IL
.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
1
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
C106–6
C106–7
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
HIGH
ADDRESS
CE
DATA OUT
V
CC
SUPPLY
CURRENT
OE
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