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參數(shù)資料
| 型號(hào)： | CY7C1223F-133AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2-Mb (128K x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 128K X 18 STANDARD SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 6/15頁(yè) |
| 文件大?。?/td> | 328K |
| 代理商： | CY7C1223F-133AC |
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CY7C1223F
Document #: 38-05418 Rev. *A
Page 6 of 15
Burst Sequences
The CY7C1223F provides a two-bit wraparound counter, fed
by A
[1:0]
, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Both read and write burst operations
are supported.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of t
ZZREC
after the ZZ input returns
LOW.
Interleaved Burst Address Table (MODE = Floating or V
DD
)
First
Address
A1, A0
A1, A0
00
01
01
00
10
11
11
10
Second
Address
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Truth Table
[2, 3, 4, 5, 6]
Operation
Address
Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
CE
1
CE
3
CE
2
ZZ ADSP ADSC
H
X
X
L
L
X
L
L
L
H
X
L
L
X
L
L
L
H
X
L
X
X
X
H
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
X
X
X
L
X
X
X
L
H
X
X
L
H
X
X
L
X
X
X
L
H
X
X
L
X
X
X
L
X
X
X
L
H
X
X
L
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
WRITE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
OE
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
ZZ Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
three-state
three-state
three-state
three-state
three-state
three-state
Q
three-state
D
Q
three-state
Q
three-state
Q
three-state
D
D
Q
three-state
Q
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW
A
, BW
B
) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BW
A
, BW
B
),
BWE, GW=H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1223F | 2-Mb (128K x 18) Pipelined DCD Sync SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1223H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 2MBIT 128KX16 3.5NS 100TQFP - Bulk |
| CY7C1231H-133AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 128KX18 NoBL FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C123-7VC | 制造商:Cypress Semiconductor 功能描述:Static RAM, 256x4, 24 Pin, Plastic, SOJ |
| CY7C1243KV18-400BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (2Mx18) 1.8v 400MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1243KV18-450BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (2Mx18) 1.8v 450MHz QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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