參數(shù)資料
型號: ADUC7032BSTZ-88-RL
廠商: Analog Devices Inc
文件頁數(shù): 78/120頁
文件大小: 0K
描述: IC MCU 96K FLASH DUAL 48LQFP
標準包裝: 2,000
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 96KB(48K x 16)
程序存儲器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 60 of 120
POWER SUPPLY SUPPORT CIRCUITS
The ADuC7032-8L also features a power supply monitor (PSM)
function. Once enabled via HVCFG0[3], the PSM continuously
monitors the voltage at the VDD pin. If this voltage drops below
6.0 V typical, the PSM flag is automatically asserted and can, if
the high voltage IRQ is enabled via IRQ/FIQEN[16], generate a
system interrupt. An example of this operation is shown in
The ADuC7032-8L incorporates an on-chip, low dropout
(LDO) regulator that is driven directly from the battery voltage
to generate a 2.6 V internal supply. This 2.6 V supply is then
used as the supply voltage for the ARM7 MCU and peripherals,
including the precision analog circuits on-chip.
Power-on reset (POR), power supply monitor (PSM), and low
voltage flag (LVF) functions are also integrated to ensure safe
operation of the MCU, as well as continuous monitoring of the
battery power supply.
At voltages below the POR level, an additional low voltage flag
can be enabled (HVCFG0[2]). It can be used to indicate that the
contents of the SRAM are still valid after a reset event. The
operation of the low voltage flag is shown in Figure 26. Once
enabled, the status of this bit can be monitored via HVMON[3].
If this bit is set, the SRAM contents are valid. If this bit is
cleared, the SRAM contents may have been corrupted.
The POR circuit is designed to handle all battery ramp rates and
guarantee full functional operation of the Flash/EE memory-based
MCU during power-on and power-down cycles.
As shown in Figure 26, once the supply voltage (VDD) reaches
a minimum operating voltage of 3 V, a POR signal keeps the
ARM core in reset for 20 ms. This ensures that the regulated
power supply voltage (REG_DVDD) supplied to the ARM core
and associated peripherals is above the minimum operational
voltage to guarantee full functionality. A POR flag is set in the
RSTSTA MMR to indicate a POR reset event has occurred.
VDD
12V
3.0V TYP
2.6V
20ms TYP
PSM TRIP 6.0V TYP
POR TRIP 3.0V TYP
LVF TRIP 2.1V TYP
REG_DVDD
POR_TRIP
RESET_CORE
(INTERNAL SIGNAL)
ENABLE_PSM
ENABLE_LVF
05
98
6-
02
6
Figure 26. Typical Power-On Cycle
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