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| 型號(hào)： | ADUC7032BSTZ-88-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 113/120頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 帶卷 (TR) |
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ADuC7032-8L
Rev. A | Page 92 of 120
High Voltage Configuration1 Register
Name:
HVCFG1
Address:
Indirectly addressed via the HVCON high voltage interface
Default Value:
0x00
Access:
Read/write
Function:
This 8-bit register controls the function of high voltage circuits on the ADuC7032-8L. This register is not an MMR and does
not appear in the MMR memory map. It is accessed via the HVCON registered interface. Data to be written to this register is loaded via
HVDAT, and data is read back from this register via HVDAT.
Table 75. HVCFG1 Bit Designations
Bit
Description
7
Attenuator Enable Bit.
0 = disable the internal voltage attenuator and attenuator buffer.
1 = enable the internal voltage attenuator and attenuator buffer.
6
High Voltage Temperature Monitor. The high voltage temperature monitor is an uncalibrated temperature monitor located on-chip
close to the high voltage circuits. This monitor is completely separate from the on-chip, precision temperature sensor (controlled via
ADC2CON[7:6]) and allows user code to monitor die temperature change close to the hottest part of the ADuC7032-8L die. The
monitor generates a typical output voltage of 600 mV at 25°C and typically has a negative temperature coefficient of 2.1 mV/°C.
1 = enable the on-chip, high voltage temperature monitor. Once enabled, this voltage output temperature monitor is routed
directly to the temperature channel ADC.
0 = disable the on-chip, high voltage temperature monitor.
5
Voltage Channel Short Enable Bit.
1 = enable an internal short (at the attenuator, before ADC input buffer) on the voltage channel ADC and allow noise to be
measured as a self-diagnostic test.
0 = disable an internal short on the voltage channel.
4
WU Readback Enable Bit.
0 = disable input capability on the external WU pin.
1 = enable input capability on the external WU pin. In this mode, a rising or falling edge transition on the WU pin generates a high
voltage interrupt. Once this bit is set, the state of the WU pin can be monitored via the HVMON register (HVMON[7]).
3
High Voltage I/O Enable Bit.
1 = re-enable any high voltage I/O pins (LIN/WU) that have been disabled as a result of a short-circuit current event (event must last
longer than 20 μs for the LIN pin and 400 μs for the WU pin). This bit must also be set to 1 to re-enable the WU pin, if disabled by a
thermal event. It should be noted that this bit must be set to clear any pending interrupt generated by the short-circuit event (even
if the event has passed), as well as re-enabling the high voltage I/O pins.
2
Enable/Disable Short-Circuit Protection (LIN).
1 = enable passive short-circuit protection on the LIN pin. In this mode, a short-circuit event on the LIN pin generates a high voltage
interrupt, IRQ3 (if enabled in IRQEN[16]), and asserts the appropriate status bit in HVSTA but does not disable the short-circuiting pin.
0 = enable active short-circuit protection on the LIN pin. In this mode, a short-circuit event causes the LIN pin to generate a high
voltage interrupt (IRQ3), assert IRQSTA[16], and automatically disable the short-circuiting pin. Once disabled, the I/O pin can be
re-enabled only by writing to HVCFG1[3].
1
WU Pin Timeout (Monoflop) Counter Enable/Disable.
1 = disable the WU I/O timeout counter.
0 = enable a timeout counter that automatically deasserts the WU pin 1.3 seconds after user code has asserted the WU pin via
HVCFG0[4].
0
WU Open Circuit Diagnostic Enable.
1 = enable an internal WU I/O diagnostic pull-up resistor to the VDD pin, allowing detection of an open-circuit condition on the WU pin.
0 = disable an internal WU I/O diagnostic pull-up resistor.
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