參數(shù)資料
型號: ADUC7032BSTZ-88-RL
廠商: Analog Devices Inc
文件頁數(shù): 38/120頁
文件大?。?/td> 0K
描述: IC MCU 96K FLASH DUAL 48LQFP
標(biāo)準(zhǔn)包裝: 2,000
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 96KB(48K x 16)
程序存儲器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 24 of 120
RESET
There are four kinds of reset: external reset, power-on reset,
watchdog reset, and software reset. The RSTSTA register indicates
the source of the last reset and can be written by user code to
initiate a software reset event. The bits in this register can be
cleared to 0 by writing to the RSTCLR MMR at 0xFFFF0234.
The bit designations in RSTCLR mirror those of RSTSTA.
These registers can be used during a reset exception service
routine to identify the source of the reset. The implications of
all four kinds of reset event are listed in Table 12.
Table 12. Device Reset Implications
Impact/Reset
Reset External Pins
to Default State
Kernel
Executed
Reset All
External MMRs
(Excluding RSTSTA)
Reset All
High Voltage
Indirect
Registers
Peripherals
Reset
RAM
RSTSTA
(Status After
Reset Event)
Yes
RSTSTA[0] = 1
Watchdog Reset
Yes
RSTSTA[1] = 1
Software Reset
Yes
RSTSTA[2] = 1
External Reset Pin
Yes
RSTSTA[3] = 1
1 RAM is valid except in the case of a reset following a LIN download.
2 The impact of RAM is dependent on the contents of HVSTA[6] if LVF is enabled. When LVF is enabled using (HVCFG0[2]), RAM has not been corrupted by the POR reset
mechanism if the LVF Status Bit HVSTA[6] = 1. See the Low Voltage Flag (LVF) section for more information.
RSTCLR Register
Name:
RSTCLR
Address:
0xFFFF0234
Default Value:
0x00
Access:
Write only
Function:
This 8-bit write-only register clears the corresponding bit in RSTSTA.
RSTSTA Register
Name:
RSTSTA
Address:
0xFFFF0230
Default Value:
0x01
Access:
Read/write
Function:
This 8-bit register indicates the source of the last reset event and can be written by user code to initiate
a software reset.
Table 13. RSTCLR/RSTSTA MMR Bit Designations
Bit
Description
7 to 4
Not Used. These bits are not used and always read as 0.
3
External Reset.
Set to 1 automatically when an external reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
2
Software Reset.1
Set to 1 by user code to generate a software reset.
Cleared by setting the corresponding bit in RSTCLR.
1
Watchdog Timeout.
Set to 1 automatically when a watchdog timeout occurs.
Cleared by setting the corresponding bit in RSTCLR.
0
Power-On Reset.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
1 If the software reset bit in RSTSTA is set, any write to RSTCLR that does not clear this bit generates a software reset.
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