參數(shù)資料
型號： ADUC7032BSTZ-88-RL
廠商： Analog Devices Inc
文件頁數(shù)： 54/120頁
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LQFP
標準包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 39 of 120
16-BIT, SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS
The ADuC7032-8L incorporates three independent Σ-Δ
analog-to-digital converters (ADCs), namely, the current
channel ADC (I-ADC), the voltage channel ADC (V-ADC),
and the temperature channel ADC (T-ADC). These precision
measurement channels integrate on-chip buffering; programmable
gain amplifiers; 16-bit, Σ-Δ modulators; and digital filtering and
are intended for the precision measurement of current, voltage,
and temperature variables in 12 V automotive battery systems.
CURRENT CHANNEL ADC (I-ADC)
This ADC is intended to convert battery current sensed through
an external 100 μΩ shunt resistor. On-chip programmable gain
means that the I-ADC can be configured to accommodate battery
current levels from ±1 A to ±1500 A.
As shown in Figure 15, the I-ADC employs a Σ-Δ conversion
technique to realize 16 bits of no missing codes performance.
The modulator converts the sampled input signal into a digital
pulse train, whose duty cycle contains the digital information.
A modified Sinc3 programmable low-pass filter is then employed
to decimate the modulator output data stream to give a valid 16-bit
data conversion result at programmable output rates from 4 Hz
to 8 kHz in normal mode and 1 Hz to 2 kHz in low power mode.
The I-ADC also incorporates counter, comparator, and accu-
mulator logic. This allows the I-ADC result to generate an interrupt
after a predefined number of conversions has elapsed or if the
I-ADC result exceeds a programmable threshold value. A fast
ADC overrange feature is also supported. Once enabled, a 32-bit
accumulator automatically sums the 16-bit I-ADC results.
The time to a first valid (fully settled) result on the current channel
is three ADC conversion cycles with chop mode turned off and
two ADC conversion cycles with chop mode turned on.
PGA
ADC
THRESHOLD
ADC
RESULT
OUTPUT
FORMAT
BUF
CHOP
ANALOG INPUT DIAGNOSTIC
CURRENT SOURCES
TWO 50A IIN+ AND IIN–
CURRENT SOURCES.
ANALOG INPUT
DIAGNOSTIC
VOLTAGE SOURCE
VREF/136 VOLTAGE INPUT.
ANALOG INPUT
PROGRAMMABLE
CHOPPING
THE INPUTS ARE
ALTERNATELY REVERSED
THROUGH THE
CONVERSION CYCLE.
Σ- ADC
THE
Σ-
ARCHITECTURE
ENSURES 16 BITS
NO MISSING CODES.
OUTPUT AVERAGE
AS PART OF THE CHOPPING
IMPLEMENTATION, EACH
DATA-WORD OUTPUT FROM
THE FILTER IS SUMMED AND
AVERAGED WITH ITS
PREDECESSOR.
ADC FAST OVERRANGE
GENERATES AN ADC
INTERRUPT IF THE CURRENT
INPUT IS GROSSLY
OVERRANGED.
ADC ACCUMULATOR
ACCUMULATES THE
ADC RESULT.
PROGRAMMABLE GAIN
AMPLIFIER
THE PROGRAMMABLE
GAIN AMPLIFIER ALLOWS
EIGHT BIPOLAR INPUT
RANGES FROM ±2.3mV TO
±1.2V (INT VREF = +1.2V).
Σ- MODULATOR
THE MODULATOR PROVIDES A
HIGH FREQUENCY 1-BIT DATA
STREAM (THE OUTPUT OF
WHICH IS ALSO CHOPPED) TO
THE DIGITAL FILTER, THE DUTY
CYCLE OF WHICH REPRESENTS
THE SAMPLED ANALOG INPUT
VOLTAGE.
IIN+
IIN–
VREF/136
GND
REG_AVDD REG_AVDD
Σ- ADC
Σ-
MODULATOR
PROGRAMMABLE
DIGITAL FILTER
OUTPUT
AVERAGE
OFFSET
COEFFICIENT
GAIN
COEFFICIENT
ADC
INTERRUPT
ADC RESULT
ACCUMULATOR
ADC
RESULT
ADC RESULT
COUNTER
THRESHOLD
COUNTER
ADC INTERRUPT
GENERATOR
GENERATES AN ADC
RESULT FROM ANY
ONE OF FOUR
SOURCES.
ADC RESULT COUNTER
COUNTS ADC RESULTS,
GENERATES AN INTERRUPT
ON COUNTER OVERFLOW.
THRESHOLD COUNTER
COUNTS UP IF ADC
RESULTS>THRESHOLD;
COUNTS DOWN/RESET IF
ADC RESULT<THRESHOLD.
GENERATES AN INTERRUPT
ON COUNTER OVERFLOW.
BUFFER AMPLIFIER
THE BUFFER
AMPLIFIER PRESENTS
A HIGH IMPEDANCE
INPUT STAGE FOR
THE PGA DRIVING
THE
Σ- MODULATOR.
PRECISION REFERENCE
THE INTERNAL 5ppm/°C
REFERENCE IS ROUTED
TO THE ADC BY DEFAULT.
AN EXTERNAL
REFERENCE ON THE VREF
PIN CAN ALSO BE
SELECTED.
INTERNAL
REFERENCE
VREF
PROGRAMMABLE
DIGITAL FILTER
THE SINC3 FILTER REMOVES
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
RATE AND BANDWIDTH OF THIS
FILTER ARE PROGRAMMABLE VIA
THE ADCFLT MMR.
DIGITAL COMPARATOR
THE ADC RESULT IS
COMPARED TO A
PRESET THRESHOLD.
OUTPUT SCALING
THE OUTPUT WORD FROM
THE DIGITAL FILTER IS
SCALED BY THE
CALIBRATION COEFFICIENTS
BEFORE BEING PROVIDED AS
THE CONVERSION RESULT.
05
98
6-
0
15
Figure 15. Current ADC, Top Level Overview
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