參數(shù)資料
型號： ADUC7032BSTZ-88-RL
廠商： Analog Devices Inc
文件頁數(shù)： 120/120頁
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LQFP
標準包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 99 of 120
UART Control Register 1
Name:
COMCON1
Address:
0xFFFF0710
Default Value:
0x00
Access:
Read/write
Function:
This 8-bit register controls the operation of the UART in conjunction with COMCON0.
Table 82. COMCON1 MMR Bit Designations
Bit
Name
Description
7 to 6
UART Input Multiplexer.
00 = RxD driven by LIN input; required for LIN communications via LIN pin.
01 = reserved.
10 = RxD driven by GPIO_5; required for serial communications via GPIO_5 pin (RxD).
11 = reserved.
5
Not Used. 0 by default.
4
LOOPBACK
Loop Back. Set by user to enable loopback mode. In loopback mode, the TxD is forced high.
3 to 0
Not Used. 0 by default.
UART Status Register 0
Name:
COMSTA0
Address:
0xFFFF0714
Default Value:
0x60
Access:
Read only
Function:
This 8-bit read-only register reflects the current status on the UART.
Table 83. COMSTA0 MMR Bit Designations
Bit
Name
Description
7
Reserved.
6
TEMT
COMTX and Shift Register Empty Status Bit.
Set automatically if COMTX and the shift register are empty. This bit indicates that the data has been transmitted;
that is, it is no longer present in the shift register.
Cleared automatically when writing to COMTX.
5
THRE
COMTX Empty Status Bit.
Set automatically if COMTX is empty. COMTX can be written as soon as this bit is set. The previous data may
not have been transmitted yet and may still be present in the shift register.
Cleared automatically when writing to COMTX.
4
BI
Break Indicator.
Set when SIN is held low for more than the maximum word length.
Cleared automatically.
3
FE
Framing Error.
Set when the stop bit is invalid.
Cleared automatically.
2
PE
Parity Error.
Set when a parity error occurs.
Cleared automatically.
1
OE
Overrun Error.
Set automatically if data is overwritten before having been read.
Cleared automatically.
0
DR
Data Ready.
Set automatically when COMRX is full.
Cleared by reading COMRX.
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