參數(shù)資料
型號: ADUC7032BSTZ-88-RL
廠商: Analog Devices Inc
文件頁數(shù): 40/120頁
文件大?。?/td> 0K
描述: IC MCU 96K FLASH DUAL 48LQFP
標準包裝: 2,000
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 96KB(48K x 16)
程序存儲器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 26 of 120
FEExHID (x = 0 or 1) is a protection MMR that controls
read- and write-protection of the Flash/EE memory code
space. If previously configured via the FEExPRO register,
FEExHID may require a software key to enable access.
FEExPRO (x = 0 or 1) is a buffer of the FEExHID register,
which is used to store the FEExHID value so it is automati-
cally downloaded to the FEExHID registers on subsequent
reset and power-on events.
Note that user software must ensure that the Flash/EE controller
has completed any erase or write cycle before the PLL is powered
down. If the PLL is powered down before an erase or write cycle
has completed, the Flash/EE page or byte may be corrupted.
The following sections describe in detail the bit designations of
each of the Flash/EE control MMRs.
FEE0CON and FEE1CON Registers
Name:
FEE0CON and FEE1CON
Address:
0xFFFF0E08 and 0xFFFF0E88
Default Value (Both Registers):
0x07
Access:
Read/write
Function:
These 8-bit registers are written by user code to control the operating modes of the Flash/EE memory controllers for Block 0
(32 kB) and Block 1 (64 kB).
Table 14. Command Codes in FEE0CON and FEE1CON
Code
Command
Reserved
Reserved. This command should not be written by user code.
Single read
Load FEExDAT with the 16-bit data indexed by FEExADR.
Single write
Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs.
Erase-write
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation
takes 20 ms.
Single verify
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison
is returned in FEExSTA Bit 1.
Single erase
Erase the page indexed by FEExADR.
Mass erase
Erase Block 0 (30 kB) or Block 1 (64 kB) of user space. The 2 kB kernel is protected. This operation takes 1.2 sec.
To prevent accidental execution, a command sequence is required to execute this instruction. This sequence is
0x07
Default command.
0x08
Reserved
Reserved. This command should not be written by user code.
0x09
Reserved
Reserved. This command should not be written by user code.
0x0A
Reserved
Reserved. This command should not be written by user code.
0x0B
Signature
FEE0CON. This command results in a 24-bit LFSR-based signature being generated and loaded into FEE0SIG.
If FEE0ADR is less than 0x97800, this command results in a 24-bit LFSR-based signature of the user code space
from the page specified in FEE0ADR upwards, including the kernel, security bits, and Flash/EE key.
If FEE0ADR is greater than 0x97800, the kernel and manufacturing data are signed.
FEE1CON. This command results in a 24-bit LFSR-based signature being generated, beginning at FEE1ADR and
ending at the end of the 64 kB block, and loaded into FEE1SIG. The last page of this block is not included in the
sign generation.
0x0C
Protect
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase
(0x06) or with the software protection key.
0x0D
Reserved
Reserved. This command should not be written by user code.
0x0E
Reserved
Reserved. This command should not be written by user code.
0x0F
Ping
No operation, interrupt generated.
1 x in the register names designates 0 or 1 for Flash/EE Block 0 or Flash/EE Block 1.
2 The FEExCON always reads 0x07 immediately after execution of any of these commands.
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