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參數(shù)資料
| 型號(hào)： | ADUC7032BSTZ-88-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 42/120頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 帶卷 (TR) |
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ADuC7032-8L
Rev. A | Page 28 of 120
FEE0MOD and FEE1MOD Registers
Name:
FEE0MOD and FEE1MOD
Address:
0xFFFF0E04 and 0xFFFF0E84
Default Value (Both Registers):
0x00
Access:
Read/write
Function:
These registers are written by user code to configure the mode of operation of the Flash/EE memory controllers.
Table 16. FEE0MOD and FEE1MOD MMR Bit Designations
Bit
15 to 7
Not Used. These bits are reserved for future functionality and should be written as 0 by user code.
6 to 5
Flash/EE Security Lock Bits. These bits must be written as [6:5] = 10 to complete the Flash security protect sequence.
4
Flash/EE Controller Command Complete Interrupt Enable.
Set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command.
Cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command.
3
Flash/EE Erase/Write Enable.
Set by user code to enable the Flash/EE erase and write access via FEExCON.
Cleared by user code to disable the Flash/EE erase and write access via FEExCON.
2
Reserved. Should be written as 0.
1
Flash/EE Controller Abort Enable.
Set to 1 by user code to enable the Flash/EE controller abort functionality.
0
Reserved. Should be written as 0.
1 x is 0 or 1 to designate Flash/EE Block 0 or Flash/EE Block 1.
FLASH/EE MEMORY SECURITY
The 94 kB of Flash/EE memory available to the user can be
read-protected and write-protected using the FFE0HID and
FEE1HID registers.
In Block 0, the FEE0HID MMR protects the 30 kB of Flash/EE
memory. Bit 0 to Bit 28 of this register protect Page 0 to Page 57
from writing. Each bit protects two pages, that is, 1 kB. Bit 29 to
Bit 30 protect Page 58 and Page 59, respectively; that is, each bit
write-protects a single page of 512 bytes. The MSB of this register
(Bit 31) protects Block 0 from being read through JTAG.
The FEE0PRO register mirrors the bit definitions of the FEE0HID
MMR. The FEE0PRO MMR allows user code to lock the protec-
tion or security configuration of the Flash/EE memory so that
the protection configuration is automatically loaded on
subsequent power-on or reset events.
This flexibility allows the user to set and test protection settings
temporarily using the FEE0HID MMR and subsequently lock
the required protection configuration (using FEE0PRO) when
shipping protection systems into the field.
In Block 1 (64 kB), the FEE1HID MMR protects the 64 kB of
Flash/EE memory. Bit 0 to Bit 29 of this register protect Page 0
to Page 119 from writing. Each bit protects four pages, that is, 2 kB.
Bit 30 protects Page 120 to Page 127; that is, Bit 30 write-protects
eight pages of 512 bytes. The MSB of this register (Bit 31) protects
Flash/EE Block 1 from being read through JTAG.
As with Block 0, the FEE1PRO register mirrors the bit defini-
tions of the FEE1HID MMR. The FEE1PRO MMR allows user
code to lock the protection or security configuration of the
Flash/EE memory so that the protection configuration is
automatically loaded on subsequent power-on or reset events.
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