參數(shù)資料
型號： ADUC7032BSTZ-88-RL
廠商： Analog Devices Inc
文件頁數(shù)： 5/120頁
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
ADuC7032-8L
Rev. A | Page 102 of 120
SPI Control Register
Name:
SPICON
Address:
0xFFFF0A10
Default Value:
0x0000
Access:
Read/write
Function:
This 16-bit MMR configures the serial peripheral interface.
Table 89. SPICON MMR Bit Designations
Bit
Description
15 to 13
Reserved. Should be written as 0.
12
Continuous Transfer Enable.
Set by user to enable continuous transfer. In master mode the transfer continues until no valid data is available in the SPITX
register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty.
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the
SPITX register, a new transfer is initiated after a stall period.
11
Loop Back Enable.
Set by user to connect MISO to MOSI and test software.
Cleared by user to normal mode.
10
Slave Output Enable.
Set by user to enable slave output.
Cleared by user to disable slave output.
9
Slave Select Input Enable.
Set by user in master mode to enable the output.
8
SPIRX Overflow Overwrite Enable.
Set by user. The valid data in the RX register is overwritten by the new serial byte received.
Cleared by user. The new serial byte received is discarded.
7
SPITX Underflow Mode.
Set by user to transmit the previous data.
Cleared by user to transmit 0.
6
Transfer and Interrupt Mode (Master Mode).
Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs when SPITX is empty.
Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt occurs when SPIRX is full.
5
LSB First Transfer Enable Bit.
Set by user. The LSB is transmitted first.
Cleared by user. The MSB is transmitted first.
4
Reserved. Should be written as 0.
3
Serial Clock Polarity Mode Bit.
Set by user. The serial clock idles high.
Cleared by user. The serial clock idles low.
2
Serial Clock Phase Mode Bit.
Set by user. The serial clock pulses at the beginning of each serial bit transfer.
Cleared by user. The serial clock pulses at the end of each serial bit transfer.
1
Master Mode Enable Bit.
Set by user to enable master mode.
Cleared by user to enable slave mode.
0
SPI Enable Bit.
Set by user to enable the SPI.
Cleared to disable the SPI.
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